Siemens Simatic S7-400 - PROFINET

Table of contents
S7-400 Automation System, CPU Specifications
vi Manual, 10/2006, 6ES7498-8AA04-8BA0
Tables
Table 2-1 LEDs of the CPUs ......................................................................................................................
2-2
Table 2-2 Faults/Errors and the reactions of the CPU ...............................................................................
2-5
Table 2-3 Possible states of the RUN and STOP LEDs ............................................................................
2-8
Table 2-4 Possible statuses of the INTF, EXTF and FRCE LEDs .............................................................
2-9
Table 2-5 Possible states of the BUS1F and BUS5F LEDs.......................................................................
2-9
Table 2-6 Possible states of the IFM1F LED .............................................................................................
2-9
Table 2-7 Possible states of the LINK and RX/TX LEDs .........................................................................
2-10
Table 2-8 Mode selector switch settings ..................................................................................................
2-11
Table 2-9 Security classes of an S7-400 CPU.........................................................................................
2-12
Table 2-10 MPI parameters and IP address following memory reset ........................................................
2-14
Table 2-11 Types of Memory Cards...........................................................................................................
2-20
Table 3-1 Properties of the CPU in the factory state................................................................................
3-12
Table 3-2 LED patterns ............................................................................................................................
3-13
Table 4-1 Communication services of the CPUs .......................................................................................
4-6
Table 4-2 SFCs for the Basic S7 Communication......................................................................................
4-8
Table 4-3 SFBs for the basic S7 communication.....................................................................................
4-10
Table 4-4 SFCs for the Global Data Communication...............................................................................
4-11
Table 4-5 GD resources of the CPUs.......................................................................................................
4-12
Table 4-6 Distribution of connections.......................................................................................................
4-21
Table 4-7 Availability of connection resources.........................................................................................
4-21
Table 5-1 41x CPUs (MPI/DP interface and DP module as PROFIBUS DP)............................................
5-2
Table 5-2 Meaning of the "BUSF" LED of the CPU 41x as DP master......................................................
5-6
Table 5-3 Reading out the diagnostics with STEP 7..................................................................................
5-7
Table 5-4 Diagnostic addresses for the DP master and DP slave.............................................................
5-9
Table 5-5 Event detection of the CPUs 41x as DP master ......................................................................
5-10
Table 5-6 Evaluation of RUN-STOP transitions of the DP slave in the DP master .................................
5-10
Table 5-7 Configuration example for the address areas of the transfer memory ....................................
5-12
Table 5-8 Meaning of the "BUSF" LEDs of the CPU 41x as DP slave ....................................................
5-16
Table 5-9 Reading out the diagnostic data with STEP 5 and STEP 7 in the master system...................
5-17
Table 5-10 STEP 5 User Program .............................................................................................................
5-18
Table 5-11 Diagnostic addresses for the DP master and DP slave...........................................................
5-19
Table 5-12 Event detection of the CPUs 41x as DP slave.........................................................................
5-19
Table 5-13 Evaluating RUNSTOP transitions in the DP Master/DP Slave ................................................
5-20
Table 5-14 Structure of station status 1 (Byte 0)........................................................................................
5-21
Table 5-15 Structure of station status 2 (Byte 1)........................................................................................
5-22