Getting Started
A5E36037886-003, 04/2017
101
p29300
Digital input forced sig-
assignment signals are forced to be high. 7 bits in total.
• Bit 0: SON
• Bit 1: CWL
• Bit 2: CCWL
• Bit 3: TLIM1
• Bit 4: SPD1
• Bit 5: TSET
• Bit 6: EMGS
If one or more bits are set to be high, the corresponding input signals are forced to be logical high signals.
The drive unit displays the value in hex format. To know the logic (high/low) assignment to each bit, you
must convert the hex number to the binary number, for example, FF (hex) = 11111111 (bin).
Digital input 1 assignment
Defines the function of digital input signal DI1 (PTI mode)
• 1: SON
• 2: RESET
• 3: CWL
• 4: CCWL
• 5: G-CHANGE
• 6: P-TRG
• 7: CLR
• 8: EGEAR1
• 9: EGEAR2
• 10: TLIM1
• 11: TLIM2
• 12: CWE
• 13: CCWE
• 14: ZSCLAMP
• 15: SPD1
• 16: SPD2
• 17: SPD3
• 18: TSET
• 19: SLIM1
• 20: SLIM2
• 21: POS1
• 22: POS2
• 23: POS3
• 24: REF
• 25: SREF
• 26: STEPF
• 27: STEPB
•
• [0]: DI1 for control mode 0
• [1]: DI1 for control mode 1
• [2]: DI1 for control mode 2
•
[3]: DI1 for control mode 3