6.1.3 The net result is the five video signals output from IC22 on pins 32, 31, 30, 12 and 11.
6.1.4 The RGB signals are fed to level-setting resistor divider network R48-R53 and a.c. coupled to RGB-to-PAL converter IC28 on pins 3, 4 and 5.
The composite sync signal CSYNC is input on pin 2. External components of the circuit provide a number of clamp circuits; the luminance and
chrominance signals are fed out, filtered and fed back in; the chrominance 4.43 crystal oscillator is connected; and a CR lead/lag network
introduces a 90° phase shift. The crystal has a very high tolerance and does not need trimming.
6.1.5 The composite PAL signal is output on pin 9, divided down and applied to an encapsulated UHF modulator M1.
6.1.6 Master clock is divided by two in IC22 from the externally connected 15 MHz crystal X1 and distributed via output pin 7 to various destinations
on the board, and to J1 the main expansion connector.
6.1.7 The system address decode signal PCENL, routed to peripheral controller ZX8302 pin 10, is derived differently on the two board versions.
On the pre-Issue 6 board it is output from ZX8301 pin 39 and is derived from a combination of one of the decodes from address lines A16 and
A17, and A14 (via DA6). In the post-Issue 6 version it is output from HAL pin 17 and is derived in a similar way from a decode of address lines
A16, A17 and A6.
6.2 ZX8302, IC23.
The ZX8302 is termed the peripheral chip since it controls all signals to and from the peripheral devices. Signals to/from the following are
supervised:
Keyboard
by serial link to IPC
Speaker
Joystick
RS232 (half)
RS232 (half)
Net
Microdrive
Real-Time clock
Interrupt control
6.2.1 IC23, in common with IC24, works autonomously and is polled by the CPU. It has its own 32 kHz crystal clock X2 and has an external interrupt
input on pin 2 from J1, the expansion connector. Switch S3 connected to pin 21 resets the device when operated. Pin 28 output resets the CPU
and IPC.
6.2.2 Address lines A0, A1 and A5 from the CPU select the specific device requiring service viz: one of (a) to (e) in paragraph 5.2 above. The
VSYNCH and PCENL signals input on pins 10 and 32 have been discussed in paragraph 6.1.1 and 6.1.7 respectively. The DSMCL signal is
discussed in paragraph 3.11.
6.2.3 Serial data from the various devices is converted to parallel data in IC23 and output to the data bus as DB0-DB7. Parallel data from the bus
is converted to serial data and routed to the relevant device for transmission.
6.2.4 The RS232 serial link, the keyboard and the joystick operation have already been discussed in the 8049µC (IC24) section.
6.2.5 The two Net jack plugs J9 and J10 are connected in the same way as in the Spectrum Interface 1 circuit. The network is common emitter in
that all stations on the network can either source current into the net or be turned off, i.e. be set in tri-state. Jack plugs are used such that those
sockets which are unused serve to terminate the network.
6.2.6 When a jack is inserted in the socket it opens up a connection to a 330Ω resistor, R15 or R16, disconnecting it from the circuit. With a
network set up, the two end stations would be the only ones with the 330Ω resistors in circuit. There is therefore their combined resistance, giving a
pull-down impedance of about 165Ω to the circuit. IC23 contains the interface and control circuitry for the network.
6.2.7 The real-time clock is run from the 32 kHz crystal X2 on pins 31 and 30. Date and time are resettable under software control. On pre-Issue 6
QLs, a trimming capacitor TC1 enabled trimming of the oscillator frequency. On the post-Issue 6 the trimming capacitor has been replaced by a
fixed capacitor.
6.2.8 The remaining lines out from IC23 are the microdrive control and data lines on pins 3, 1, 19, 21, 33 and 34. These inputs and outputs are
discussed in Section 7, MICRODRIVE.
7. MICRODRIVE
7.1 Introduction
7.1.1 Microdrive organisation and control in the QL is similar to that found in the Spectrum, bearing in mind that the two QL microdrives are
integrated into the system and that Interface 1 functions are all executed by IC23; also the frequency is different and write protect is different.
7.1.2 Additional microdrives may be connected to the system via connector EC1.
7.1.3 Only one microdrive may be in use at any instant. The required microdrive and the type of operation, read or write, is selected under software
control. During a read operation data is read from the selected microdrive tape. During a write operation the microdrive tape is erased before
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