SECTION 1
SYSTEM DESCRIPTION
LIST OF CONTENTS
1. Introduction
2. Architecture
3. MC68008 CPU
4. Intel 8049 Intelligent Peripheral Controller (IPC)
5. Memory Organisation
6. Peripheral Control (ZX8301, ZX8302 and IC28)
7. Microdrive
8. Power Supplies
9. Test
RS232 Link
Keyboard Matrix Interconnections
QL Block Diagram
QL Circuit Diagram (Issue 5)
QL Circuit Diagram (Issue 6)
1. INTRODUCTION
1.1 The QL computer can be regarded in hardware terms as a combination of an enhanced Spectrum microcomputer, an Interface 1, an Interface 2
and two Microdrives within the same case. In practice the resemblance to the Spectrum is small, since the QL requires two microprocessors to
accommodate powerful new software and is provided with 128k bytes of inbuilt DRAM. A block diagram of the Sinclair QL is given in Figure 1.3.
1.2 Two main versions of the QL are in circulation. A certain number of boards to build standards up to Issue 5 were issued in either ROM or
EPROM versions with another ROM mounted pickaback in IC33 position. The second, volume production, version of the board to build standard
Issue 6, and subsequent, features 48k of on-board ROM realised in two memory devices. In the following description the two versions are referred
to as the pre-Issue 6 and the post-Issue 6 versions. The main differences between the two versions, as far as the circuit description is concerned,
are that IC17 and IC27 have been deleted and IC38 added in the post-Issue 6 version.
2. ARCHITECTURE
2.1 The architecture of the QL shown in Figure 1.3 incorporates much that is typical of microcomputer systems, but certain innovations make it
atypical. Two microprocessors, an Intel 8049 and a Motorola 68008 are used, and the availability of 128k of DRAM plus a minimum of 200k on the
two microdrives provides unusual storage facilities. The 8049 is designated the Intelligent Peripheral Controller (IPC) and the 68008 is the CPU.
Two additional semi-custom ICs ZX8301 and ZX8302 control defined areas of the system, under the supervision of the CPU.
2.2 The microcomputer electronics are housed on a single printed circuit board which also houses a regulated power supply fed from an external
power unit. The keyboard forms part of the upper case assembly and is connected to the p.c. board via J11 and J12. The microdrive headboards
and microdrive chassis, including the microdrives and the motors, form two complete sub-assemblies which plug in to the main p.c. board.
2.3 To the rear and side of the case are plug assemblies which accommodate the following:
1. main expansion connector, J1
2. ROM cartridge, J2
3. joystick, J3, J4
4. RS232, J5, J6
5. extra microdrives, EC1
3. MC68008 CPU
3.1 The Motorola MC68008 is a 32-bit microprocessor with an 8-bit data bus and is responsible for the overall timing and control of the QL. The
firmware, which is outside the scope of this manual, resides in either a ROM or an EPROM depending on the version. The 68008 has an external
clock, generated by the ZX8301 and has the usual bus input/output arrangement, viz. data bus, address bus and control bus. It operates semi-
synchronously in this configuration.
3.2 Data Bus. D0-D7 forms an 8-bit bi-directional data bus with active high, tri-state outputs. It is used for data exchanges with the memory, with the
ZX8302 and ZX8301 and with the peripherals.
3.3 Address Bus. Twenty bits A0-A19 are available for select and address purposes. A0-A15 form a 16-bit address bus with active high. The
address bus provides the address for memory (up to 128k bytes) data exchanges and for data-exchanges with the QL and microdrive. Three bits
A0, A1 and A5 are used for this latter purpose. Bits A16-A19 are used for device selection.
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