being written. The erase head is displaced from the write head and is timed by IC23 to sink current before the write head is enabled.
7.2 Microdrive Selection
7.2.1 Microdrives are selected using the MDSELDH and MDSELCKN signals from IC23. Each microdrive control chip, IC29 and IC30, contain one
stage of a shift register, realised by a flip-flop. MDSELCKN is connected to each microdrive and MDSELDH is routed to pin 22 (COMMS IN) of
IC29, which is the input to the shift register. The shift register output on pin 20 (COMMS OUT) is routed to COMMS IN in IC30. COMMS OUT on
IC30 pin 20 is routed to microdrive expansion connector EC1. The selected microdrive has a '1' on its COMMS OUT pin. Thus the required
microdrive is selected by shifting the '1' accordingly.
7.2.2 COMMS OUT not only feeds the next microdrive; it is used to select its own chip internal functions and to select the LED, the motor, and the
erase current for the selected microdrive. Therefore while this signal is low the motor is disabled, the LED is off, no current can flow through the
microdrive switch (S1 or S2), and no erase current can flow.
7.2.3 Consider the motor drive circuit for number 1 motor. A high on pin 20 of IC29 turns on TR4. This pulls the base of TR6 low, turning it on and
switching power to motor 1. Capacitor C21 and resistor R28 time constant ensures that the motor does not cut out too quickly and damage the
tape. The red LED D20 is switched on at the same time. With TR6 turned on and write protect switch S1 closed the erase head current circuit is
enabled via pin 6 of headboard 1 connector. When the erase output is enabled on pin 1 of IC23, transistor TR3 switches on and current flows in the
selected microdrive erase head. Diodes D18 and D16 provide protection against reverse currents. Diodes D12 across the erase head and D15
perform similar functions. The amount of current flowing in the erase head is limited by R25.
7.2.4 Write protection is achieved by the action of the microswitch on the microdrive chassis. The switch is operated by the write protect tab on the
microdrive cartridge. When the tab is present the select supply line is connected to the erase coil, enabling the QL to write normally. When the tab
is absent, the supply to the erase head is disconnected, and the MDRDWL line is held high (read mode) via R100/101 and D22/23 (see Section 5,
para 3.1). This line is clamped to 5 volts maximum by diode D29. The purpose of D22/23 is to prevent unselected microdrives with no cartridge
inserted (or with writeprotected cartridge inserted) from loading the MDRDWL line.
7.3 Read/Write Operations
7.3.1 The MDRDWL signal on IC23 pin 3 places the selected microdrive in either the read or the write mode, and enables the read or the write
amplifiers.
7.3.2 Data is recorded on two tracks using a standard stereo cassette head arrangement and is written in bytes, one byte to one track and the next
byte to the other track. It is recovered in the same way. The tape itself is one continuous loop. Since hardware takes care of switching between
tracks the software sees the tape as one doublelength single track.
7.3.3 Power to the microdrive circuits has to be filtered and IC31 and capacitors C9 and C11 are used to accomplish this. IC31 is the regulator.
7.3.4 Read Cycle. Consider IC29 and headboard 1. In the read mode the signals appearing in the two read coils inside the heads are differentially
amplified through two amplifier chains within IC29. The signals are then converted to digital form to enable logic processing. The outputs from the
two amplifiers, in digital form are enabled into the DATA 1 and DATA 2 outputs from IC29 on pins 24 and 19. These signals are routed to the
interface within IC23 via RAH (Read and Write) 1 and 2, pins 21 and 19.
7.3.5 The signal recorded on magnetic tape is at the greatest when the rate of change of the signal imposing it is at its fastest. Therefore when a
squarewave has been written, the greatest recovered voltage is obtained on the edge of the pulse. Since the object of the exercise is to produce a
waveform which changes at the peaks of the recovered signal, IC29 contains amplifiers to bring the signal up to the required level, and a peak
detect circuit which changes state when the input reaches its greatest level. The peak detector is followed by a hysteresis circuit which ensures that
the output does not change on spurious signals.
7.3.6 The gain of the circuit should not need to be changed, as only one type of high quality video tape is used. The reproduced signal levels may
be read across capacitors C15 and C17 and are typically in the order of 400 to 500 mV and 250 to 350 mV for the low frequency and high
frequency signals respectively. In the record mode the modulator in IC23 converts the ones and zeros in the data into FM (frequency modulation)
where there is always a transition at the beginning of the bit cell. If the data is a one there is a transition at the beginning and in the middle of the bit
cell, which means essentially that the frequency doubles if the data contains ones. Hence high and low frequencies at C15 and C17.
7.3.7 Write Cycle. When the MDRDWL signal from IC23 goes low the selected microdrive is placed in the write mode. This has the effect of
changing DATA 1 and DATA 2 on IC29 from outputs to inputs. These inputs are used to drive current sources for track 1 and track 2. When DATA
1 is high for example, current is pulled in one direction through the head, when it is low current is pulled in the other direction.
8. POWER SUPPLIES
8.1 A custom-built power pack, external to the main board, supplies 9 volts d.c. at 2 amps and 44 volts peak-to-peak a.c. to the board input on
connector J3. The power pack uses a thyristor to limit peak voltages on the d.c., but is otherwise unregulated and has significant ripple.
8.2 The a.c. input is applied to two rectifiers IC37 and IC36 to produce +12 volts at 80 milliamps and -12 volts at 50 milliamps, respectively.
8.3 The d.c. input is regulated down to +5 volts by regulator IC35.
8.4 All three supplies are completely protected in that the regulators are equipped with thermal and short circuit shutdown.
9. TEST
9.1 A good simple test of the equipment may be carried out by connecting a loopback cable to the RS232 interface connectors J5 and J6 and
instructing them to talk to each other. The technique for receiving RS232 involves the data passing through the IPC, through ZX8302 and back onto
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