the loudspeaker. The loudspeaker is damped by resistor R104 (post-Issue 6 only).
5. MEMORY ORGANISATION
5.1 Introduction
5.1.1 The pre-Issue 6 version was supplied in both EPROM and ROM forms with on-board straps enabling the selection of ROM. Both versions
have 48k of ROM and in both versions there are 128k bytes of RAM memory. Figure 1.3 shows how the memory is organised.
5.1.2 The lower 48k bytes (addresses 0000-BFFF) are implemented in one 32k and one 16k byte ROM, IC33 and IC34 respectively which hold the
monitor program. This program is a complex 68008 machine code program divided broadly into two parts: the operating system and the BASIC
interpreter. Details of the program content are outside the scope of this manual.
5.1.3 32k bytes of memory (addresses C000-FFFF) have been left assigned to the ROM cartridge while 128k bytes of RAM (addresses 20000-
3FFFF) are implemented on sixteen 64k-bit dynamic RAMs, IC1-IC16.
5.2 Read/Write Operations
The following description should be read in conjunction with the circuit diagrams given in Figures 1.4 (pre-Issue 6) and 1.5 (post-Issue 6).
5.2.1 Read Only Memory. The CPU addresses the ROM/EPROM directly during memory read cycles using the address bus A15-A0. In the pre-
Issue 6 version, depending on the ROM/EPROM fit, the enabling and selection pins on IC33 and IC34 are set by link selection on IC17. Links JU1
to JU6 via gate circuit IC17 are used to provide the correct signals; the link fit requirements for different ROM/EPROM versions is listed on the
circuit diagram, Figure 1.4. In the post-Issue 6 version the ROMs are enabled directly by the signal ROMOEH from ZX8301.
5.2.2 RAM Memory (IC1-IC16). The sixteen RAM ICs making up the 16k x 64 bit RAM memory are organised as two matrices of 256 rows x 256
columns i.e. IC1-8 and IC9-16. Thus, separate 8-bit row and column addresses are required to access any one of the 64k locations in each
section. These addresses are supplied by the CPU (68008) on address bus A0 to A15 via tri-state address multiplexers IC19 and IC20. These
multiplexers decode from sixteen to eight lines and outputs enabled by the row address select line (RASL) signal from the ZX8301. The valid data
address (VDA) selects the address from the CPU (via multiplexers IC19, IC20) or from the ZX8301. ROWL from the ZX8301 selects the
row/column address. The R/W signal from the CPU informs the ZX8301 to expect either a read or a write cycle. For a write cycle the ZX8301
enables the write enable (WEL) line to the memory.
5.2.3 The eight bits each of column and row address are routed to both 64k sections of the RAM but the signals 'column address select 0' (CAS0L)
and 'column address select 1' (CAS1L) from the ZX8301 ensure that only the required half of the memory is active. Address bits A16 and A17 from
the CPU are decoded by the ZX8301 to enable the relevant CAS signal. The row address select line (RASL) signal from the ZX8301 is enabled
during all read and write cycles from RAM.
5.2.4 The ZX8301 has priority when accessing memory since it must access the memory mapped display area in the RAM at set intervals in order
to build up the video for the TV display. When the ZX8301 requires to access memory, it asserts the VDA signal to CPU address multiplexers
IC19, IC20 and addresses RAM directly via its own address bus on pins 13, 17, 18, 20, 22, 24, 27 and 28.
5.2.5 Isolation between the two data busses D0-D7 and DB0-DB7 is accomplished using bus transceiver IC21. During ZX8301 memory cycles
IC21 is disabled by negating the signal DEL from Hard Array Logic (HAL) IC38. This signal is controlled by ZX8301 signal TXOEL. In the pre-Issue
6 version, which does not incorporate the HAL, TXOEL is fed directly to IC21.
5.2.6 Refresh for the DRAM memory is accomplished during normal read cycles i.e. most rows are refreshed each time the ZX8301 accesses the
memory mapped display area during picture compilation, the remaining rows are refreshed as a result of other read cycles also known to occur at
regular intervals within the refresh period.
6. PERIPHERAL CONTROL (ZX8301, ZX8302, IC38 and IC28)
6.1 ZX8301, IC22.
The ZX8301 carries out the following functions:
1. TV picture generation
2. master clock generation
3. system address decode
4. DRAM refresh
5. control of the bus transceiver.
6.1.1 The TV picture generation section of IC22 operates in conjunction with the memory mapped picture display area to produce five colour TV
signals suitable for driving a colour monitor. These signals, red, green and blue (RGB), CSYNCL (composite sync) and VSYNCH (vertical sync) are
routed to connector J7. The RGB and CSYNCL signals are also input to IC28 which produces composite PAL to drive a domestic TV receiver. The
same signals are mixed in transistor TR9 to produce a composite video signal to drive a standard monochrome monitor. VSYNCH is also routed to
IC23 where it is used to provide an interrupt at the frame rate. This is used to give a time reference to the job scheduling supervisor in the operating
system.
6.1.2 Using the 15 MHz crystal clock, X1, IC22 derives line and field timing compatible with the external receiver. Video is derived by accessing the
memory mapped display area in the RAM in a set sequence at set times throughout the picture frame. The addresses are necessarily independent
of the CPU and appear on IC22 address lines DA0 through DA7.
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