Standalone Mode
4
40
The following diagram illustrates the timing for the Low-Level Interface signals.
PRJ_SELx
START_ENAx
START
BUSY
OK/ERRx
PRJ_SELx and START_ENAx lines are sampled at the START falling edge,
and must remain stable until BUSYrising edge
OK/ERRx lines become valid at the
BUSY falling edge
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Low-Level Interface Signals Timing
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