Sony CDP-3100 - Page 59

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Description of CDP-3100
The compact disc player CDP-3100 for business use consists
of the following seven boards. (Excluding optional boards.)
e AU-183 board (System control section, clock and audio
circuits)
e SV-145 board (Servo control section)
e AC-146 board (Power supply)
e DSP-52 board (Display and function keys)
e CN-812 board (Output connector)
e JK-43 board (Headphone amplifier)
¢ MB-508 board (Mother board for optional I/F board)
AU-183 board
1. System control section
The system control section consists of V25 CPU (ICB8),
address decoder (ICD6, ICD7), 128 kbyte ROM (ICB10), 32
kbyte RAM (ICE10), interrupt controller (ICE8), interval timer
(ICD8), keyboard display VF (ICE3), parallel /O (ICES), etc.
The system clock of the CPU ts 8 MHz (16 MHz frequency
divided by two). The CPU (ICB8) has two senal /O systems.
One ts used for communicating (38.4 kbits/sec) with CDS-
3100 and the other is used for interfacing with the digital
signal processor IC of the SVB-145 board, servo signal
processing IC, VARI PLL (ICN4), and non-volatile RAM
(ICD4) via the serial /O switcher (ICB4, ICC4). The servo
status signal from the SV-145 board ts directly input to the
parallel port of the CPU (ICB8).
The key switch information from the dip switches (S2, $101)
and DSP-52 board is input to the CPU (ICB8) via the
keyboard display I/F (ICES).
As to the LEDs on the DSP-52 board, the dynamic lighting ts
performed by the keyboard display V/F (ICES), while the LEDs
of the STOP, PLAY, and STAND BY keys perform the static
indication by ICs E6, E7 and F7 to increase the luminance
level.
As to REMOTE-3, information is input by the keyboard
display I/F (ICE3), and the TALLY output 1s made by the
parallel VO (ICES).
The system control section also functions as an interface with
the optional memory board (DABK-3101) and I/F board
(DABK-3102 or DABK-3103)
2. Clock circuit
The 22.5792 MHz clock (512 times of the 44.1 kHz sampling
frequency) oscillated by the crystal oscillator (X301) 1s input to
the VARI PLL (ICN4) The Fs variable 512 Fs 1s generated
here. The clock selector (ICL4) is used for switching the clock
when optional I/F board carnes out the external
synchronization
The 512 Fs is transmitted to the SV-145 board via ICM3, the
delay line (ICK3) for matching tts phase to that of the Fs signal
input from the SV-145 board, and clock frequency dividing
circuit (ICP3, R3, S3, S4, and T3) via ICM3. Vanous clocks
such as 256 Fs, 64 Fs, Fs, etc. are created from tt.
These clocks and the audio data are transmitted to the digital
filter (ICH8), digital output (ICF10) and optional board
connectors (CN104, CN113) after their timings are matched
by ICS5, T4, and T5.
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3. Audio circuit
The audio data 1s converted to the analog signal ia the digital
filter (ICH8) and D/A converter (ICJ8), passed through the I/V
converter (ICK7, ICK11), LPF (ICM7, ICM11), de-emphasis
amplifier (ICL7, L10, N7, and N10), on-line switch (ICN6,
ICNQ), ine amplifier (ICP7, P10, R7, and R10), and CN108 to
CN-812 board, and output from the line output connector
(CN145, CN146).
Before it is de-emphasized, the analog signal is passed
through buffer amp (ICK6, K10), and transmitted to the
optional board via MB-508 board from CN111 and CN112.
After it is de-emphasized, the signal is passed through the
monitor amplifier (ICM8) and CN109 to CN-812 board, and
output from jack J1 for monitor output At the same time, it is
also passed through CN110 to the headphone amplifier of the
JK-43 board and output from the headphone jack J1.
DSP-52 board, JK-43 board, CN-812 board, MB-508 board
The DSP-52 board consists of the switches (S1, S3 to S7) for
key inputs, 7-segment LEDs (ND1 to ND4) for displaying the
disc data (time information, etc.), and LEDs (D1 to D13, D15,
D19, D20, D22 to D25, D27 to D30) for status indication.
The JK-43 board consists of the headphone amplifier (IC1),
level vanable control, and output jack
The CN-812 board relays the input/output signals of the
connectors and switches the output level
The MB-508 board is the mother board for optional I/F board
SV-145 board
The RF signal read from the mechanical deck CDM19A-6FA
is passed through the EFM comparator (ICC3A), and
decoded and error corrected by the digital signal processor
(ICC2A).
The audio data 1s output to the AU-183 board from CN3.
The focus error signal FE and tracking error signal TE are
processed by the servo signal processor (ICF2A), passed
through the dnver ICF4A to control the biaxial device of the
optical pickup inside the mechanical deck.
The linear motor is controlled by ICD4A, D4B, F2A, F3A, and
F4A.
The spindle motor ts controlied by ICC2A, F2A, and F4A
When the disc is started up and during search, serial
commands are sent from the CPU of the AU-183 board to the
digital signal processor (ICC2A) and servo signal processor
(ICF2A) to control this board via the dnver. Loading and
unloading is carned out with the parailel port of the CPU via
the loading dnver (ICA5B)
The sub-code information (time information, etc ) on the disc
1s decoded by the digital signal processor (ICC2A) and read
by the CPU using the senal I/F
The SV-145 board also has a delay line (ICB3A) for matching
the phases of the 512 Fs clock and Fs clock inside the AU-
183 board and dropout compensating circurt (ICE1B, F1B,
and G1B) in the frame sync signal dunng playback.
4-3