Sony CDP-3100 - Page 60

74—-HALF—-HSFEBLE
RS
y
FY
ILS—-BSTEI
Y—
RES
MBICAIC
£ DMB
SH,
FSA
ICRALE
LTR
AF
IF
AOHZUCYVIT
y
FOWMF
INA
AeAY
h
u—jy
LTS,
Y=7E—FIk,
ICD4A,
D4B,
F2A,
F3A,
FAA
LO
IY
b
U—-WwSHTWS,
AEY
FIE—Fid,
ICCA
FPA
FAAS
OY
bO-Ws
NTS
FAAT
ORD.
BLOET—F
BIL,
AU-183HROCPUD
BF
479
MES
MBICQA),
+
KES
MBICRAICY
UT
MEGeeent,
FIANEBBL.
ay ho-—ws
NCS.
O-
FAY
-
7
yva—F4
YF
HKEIL,
CPUD
NIVNME-
bo
FH
4
YI
EDA
/NICASB)EMLT
Ffo
TWAS.
Ek,
Ft
A7TAOYTIA—
FRM
IT
1 VF
WES
MBICQA
TF
IA—
FAH,
CPUMBY)
7 VLY/FE
AAV
CRAWL
TWS,
SOI,
FEBROTL—-ASYNCESOXRSREOR
CICE1B,
F1B,
G1B)
¢
AU-1832RAO512Fs7
Uy
7
EFs7
Uy
7
ORLBADLERS
HOOF
4
V4
54
YACB3A)A
bS.
AC-1462845
ACT YL» hPOBBAA yp FERLT. CNIONZADE
RREAC—RKML.
T1CwW,
ULL
ZIAY
IANS
EY,
CN163(J,AE)% 721i, CN164(UC, UK, EK) 5 BRS > Alc
AD, 2RACHEKBREH, CNIOIE DADSHS.
D355i= EO BFS Ne+15Vid, EOF ECDS-3100) E— }
IY hU-SACERERSZLE SIZ, CP351ICE N45V0*
EER SAL, D360,Q351I L N+8VAE MAH,
E27, D356~359 LY VHS, D361, Q352iC £ H-BVATE
MSN. D3S1~354I2 4h BH SH, 10351, 352K LO 7 FU
FALISVPERSHS,
AC-146 board
The
primary
AC
line
input
to
CN162
from
the
AC
inlet
via
the
power
supply
switch
is
passed
through
the
line
filter
(T1,
C10,
and
C11),
input
to
the
power
supply
transformer
from
CN163
(J)
or
CN164
(UC,
AE,
UK,
EK),
converted
to
secondary
AC
voltage,
and
input
from
CN161,.
The
+15
V
rectified
by
D355
is
used
as
it
1s
for
the
CDS-3100
remote
controller,
used
by
CP351
for
creating
the
+5
V
and
by
D360
and
Q351
for
generating
+8
V
It
is
also
rectified
by
D356
to
D359
and
used
by
D361
and
Q352
for
generating
-8
V,
and
rectified
by
D351
to
D354
and
used
by
1C351
and
1C352
for
generating
the
analog
+15
V
2. DABK-3101 (MEM-542¢4h) GIR etSe
MEM-S42t4R ISEB X EY BBW, WY VRVOF IVY
WA- FP 4ASO, AEY-VaFRALIVIRAI—b#B
HEX 4TF.
BBs, XEY-AY hU-WVeEF5LSIICE3), t-F AF
T— 9 FA256K X4E y b ODRAMBECCGIA, GIB, G2A, G2B,
G3A, G3B, G4A, G4B), CDF I—-F¥—TFHI— FARKRFY
FWVOZ2EY hAUY b/CHEIGEY KADY K/CHKE
RI ZA0y b SRBC, AS, BS, A4,B4), YaFoe
&O/*\) BE AADSPACDS), DSPHDTAAEOMBAKSE
DNF -FAUY bEROYILVYAZACCS, C4). 7
Uy 7 BdCA3, B3). AKCPUADRAMETILATFSE
SISDRAMI Y KU—WLSIL OM ARETE CVT bA
¥ }O—JVBIRICAL, A2,B1,DDP523,
CN-2100 12B3§F(DATAIN) 25 ADS 17232" y b /CHO
FIIWA-F AFF —FlZATY bARBPACA, AS, BS,
A4, B4)T16¥ yy AYCHKADY KBREKH, AEY-—Ay
hu 2475 LSI (CES) KH S5hH, DRAMI BL 5NS,
XAEY—-IAY bU—IWLSI (ICE3)iSCPUS ATMEL THE
CPUS & DIBA CDRAMPS FYI WA-FAAF—-P RH
AHL. DSPSDOMFIZ32Ey b //CHMOAUY KTHAL,
RRODSP ICD5)\3K%KS. TMDER, FYPWA-F AF
F-FiMEAOGEY bKHESNS, ¥HTRGSDOMT
PHS = TEHEORICS|S SM TDRAMS ORAL SH
2TLIWMA-FAAESLANTSROOF—F B32EY
b/CHOAU y hCHEDOGE » b (CHES TDSP ACD) OD
b5-—ODADICHT.
DSPIZICE3DCPU/DSP1 YI —-7 et AL MBCTHUPS
GASH. AD ENRF—FEFVINVMBL, 224 bY
CHAU Y hOMFEROIGEY MEF YI WVA-FAAF—-F
ZEHDTS. CMESUKNEMIGEY hYTIhVYAYH
CC. BEDE Y SY NA-F AAT A— Ty PICS RI, 32
Ey h/CHDRAZ#FOGEY bILY Tb EH, CN210D
12C DATAOUT) FHA SHS,
FAUSBGE AR O32Fs, 64FsiZICE3ic £ 0 256Fs & LRCK (FS) 5
TEORSA, 32K > h/CHPOI6EY b /CHAOFRE
FR/V
AILDFF
(ICA3)
EEXOR4’—
hCACB3)IC
£
OSH
do
CN2109 16C¥-F (NORMAL MEM * {3-3 )ik MEM-5422 4 2°
RRSNTVIBU, BAOF YS VA-FAAEBTIAY
=MEM-S4A DAD FY ENASHHETFSROOLVYATA
yeRoTwS,
Description of DABK-3101 (MEM-54 Board)
The MEM-54 board carnes out the memory jog and quick
Start functions for the 2 channel digital audio signal by using a
semi-conductor memory.
The circuit is made up of the followings.
e LSI (ICE3) for memory control
e Eight 256 k x 4 bit DRAMs (ICG1A, G1B, G2A, G2B, G3A,
G3B, G4A, and G48) for the audio data
e Slot conversion circuit (ICA3, A5, B5, A4, and B4) for
converting the digital 32-bit slot/CH decoded by the CD
decoder into the 16-bit slot/CH.
e Vanabie-pitch playback DSP (ICDS) in jogging
e Data slot conversion shift register (ICC5 and ICC4) for
transmitting the DSP output to the circuits of the main unit.
¢ Clock circurt (ICA3 and ICB3)
e Wart control circurt (ICA1, A2, B1, and D1) for preventing
concurrence with signals from the DRAM control LSI in the
bus when the main unit CPU accesses the DRAM
The 32 bits/CH digital audio data input from the 12B terminal
(DATAIN) of CN-210 is slot-converted into 16 bits/CH by the
slot conversion circuit (ICA3, A5, BS, A4, and B4), transmitted
to the LSI (ICE3) which controls the memory, and stored in
the DRAM.
The memory control LS! (ICE3) ts instructed by the main unit
CPU, via the CPU bus, to read the digital audio data from the
DRAM, to output it to the DSPSDO terminal in the 32 bits/CH
slot, and to transmit it to the DSP (ICD5) in the next stage.
The digital audio data is put on the former 16 bits at this time.
The data for interpolating the digital audio signal that has
been thinned out dunng jog operations and read from the
DRAM is put on the former 16 bits in the 32 bits/CH slot and
output from the TRGSDO terminal to the other input of DSP
(ICD5).
The DSP is controlled from the CPU wa the CPU/DSP
interface (ICE3). The input data is digitalized and a digttal
audio data is output to the former 16 bits of the 32 bits/CH
slot. To match the digital audio format of the main unit, this
signal is shifted to the latter 16 bits of the 32 bits/CH slot by
the 16-bit shift register in the next stage, and output to 12C
(DATAOUT) of CN210.
The 32 Fs and 64 Fs for interna! control are generated by the
256 Fs and LRCK (FS) by ICE3. And the pulse for controlling
conversion from the 32 bits/CH to 16 bits/CH 1s generated by
the DFF (ICA3) and EXOR gate (ICB3).
The 16C terminal (NORMAL/MEM#signal) of CN210 is used
as a sense kine for inking the digttal audio signal line of the
main unit by passing the MEM-54 board connector when the
MEM-54 board is not mounted.