Sony CDP-3100 - CDS-3100 Block Diagram and Description

CDS-3100
TEST SW
CS
I
| ‘say D10 Q31,I1CAS
be-pe +5v
' CONVERTER $7
CDS-31 00EI ZO
CDS-31001ZCDP-31002 VANZ KFA RIT VAV—-BAOD
JYE-hAYhKU-FCHY), UF OSERCHERSNTH
Bo
*KC-302R(YAFAIYO p—I)
HA-7EMR(AY FRY TY TZ)
*
LED-182K(F
4
AY
FH—4F
KR)
> KY-2522R(F—-—V bY ZR)
* IK-40ZR(N 9 FRY YZ - VR)
'
|
|
ices HBS ig) Seca
1CAa 8s
FILTER
aes
(0)
cues
|
eae
"
'
VeVYUNR WIRUNAM VU Iirils
| CDS-3100
1eB2 Dé D7
ee ey antes
cuso2
COUNTER SNist NDi~s
G23~30
DISPLAY
DRIVER
NOS O11~11
7SEG LEO(FRAME)
1 LE D- 1 4 8 LEO MATAIX
Q9~22 1¢C
PIO
ORIVER
LED
DRIVER
OVERALL sLock DIAGRAM
CDS-3100
Description of CDS-3100
CDS-3100 is a remote controller exclusive for CDP-3100
compact disc player. CDS-3100 consists of the following five
boards.
e KC-30 board (System control)
e HA-17 board (Headphone amplifier)
e LED-148 board (Disc data indication)
e KY-252 board (Key matnx)
e JK-40 board (Headphone jack, VR)
7SEG LED
(TNO INDEX MIN SEC) 1
KC-30224K
YAFAAY bU—NBILZIOM1F y FCPUGCCS,. FF
AF A— F1CB7, D6, D7), 32k/*4 KROM(CB6), 8k7*4 b
RAM(CC7), 7°97 VIVL/OUCC3)Fle tL ORMENTVIS~
CPUDYAF AZ UY Zid, 9.83MH222549 b724.915MHz
Cth be
CDP-3100I3¢ L Tid, CNIOI THRESH, EIS VT
(38.4k bitsec)C FF 4 — + VY —-NACDINEMLT, ICCS
DYVTM/OKTHONTWS, EB, BEHOZ-077
ta. CPUZ Uy 7 ECPUNRAYD YI CHALTHOTY
bo
H—-AA VARIA, FTV IY as YF—-G1I~DBEUOKY-
W2HRAD + —(S6~2N TV AUAALHRL, NFL
/ OACC3)EB TCPUACCS) ARO AATWIS, BAICBLT
ia. 7ryv7yYa YX—(S1~5)MLEDISCPUACCS) DA — b
CAIFAYIT AREF, LED-1488KS L UKY-252H MK
AQDIXZ AXY LED, AF —F ARFLEDIZ, NFVIMY
OUCC3I BLUE F4AN—-(QW~3HiLOFA TS YA
RI oOTWS.
JOGY AV VPSOMER WAL YaF AVY FACB2E
EB LTCPUACCS)IKA DENS,
Bix, CDP-31004 0 AW SNK+15VRODCDCIY7t—
¥ (D10, Q31, ICA3)Ii L OASVEARL, Va THAW,
HA-172RIC 4 HBLTS,
LED-14828iR. KY-25224R
LED-1482HIF 4 AZT F—F (BMRB LRRTSrH
DICT XY bLEDNDI~5) & AF — F ABFA OLEDD1~
11) THRENTVS.
KY-2522ERIk¥— AD BOAL y F(S6~29) BKU SKIPHH
4EXZTRLED(D30) THALES NTVS,
HA-172048. JK-402EiR
KC-302R9 bY —/NSICDDTHBABLTAH SN, AES/
EBUZ t—Vy hDFYVINA-FAAF—-FlZ, FVIN
AFICACABINE LO FA- FSH, FYINWI4 VF ACB)
CADEHS, ICB1, BAF WY PERO DOPLLOU—
RATA NIBELUVCOTHS.
FIINI4WVIACBDKEL OLY TY YA SA AERES
RI, FYI NMF—F id, D/AIYIN—FACAS)IEL OTF
OF ES ICERSEN. Ay FRY TY TICBNELTIK-40
BRONY FRYY YY FIDE OMASNS!, EBL A~AY
FRYT Y TACBNIZB—BHBHETS 9. IK-AORMOY
DARVDOIEYBLUY + y FQNNAEYIGNDEMT
Bev,
Ek. DAADYAN—FACAS). Ay FRY TY FICBNOE
WUICCIIC L OAR LAT TOS ROS VEBALTOS.
KC-30 Board
The system control block consists of the Z80 system 1-chip
CPU (ICCS5), address decoder (ICB7, D6, and D7), 32 k byte
ROM (ICB6), 8 k byte RAM (ICC7), parallel /O (ICC3), etc.
The system clock of the CPU is 4.915 MHz (9.83 MHz
frequency divided by two).
This board is connected te CDP-3100 through CN101.
Communication is made in senal (38.4 k bits/sec) and ts
carned out by senal I/O of ICC5 via the dnver receiver (ICD1).
The CPU clock is frequency-divided by the built-in CPU
counter to use as a communication clock.
The key switch information ts input by the CPU (ICC5) via the
parallel I/O (ICC3) by forming a matnx using the function keys
(S1 to S5) and the keys (S6 to S29) of the KY-252 board As
to indication, the LEDs of function keys S1 to S5 carry out
static lighting on the CPU (ICC5) port The 7-segment LEDs
and status indication LEDs of the LED-148 board and KY-252
board carry out dynamic lighting by the parailel I/O (ICC3) and
the dnver (Q3 to Q30).
The rotation pulse from the JOG dial ts input to the CPU
(ICC5) via jog counter (ICB2). The power is supplied to the
jog dial and to the HA-17 board by generating +5 V from +15
V that ts input from the CDP-3100 via DC-DC converter (D10,
Q31, ICA3).
LED-148 Board, KY-252 Board
The LED-148 board consists of the 7 segment LEDs (ND1 to
ND5) and status indication LEDs (D1 to D11) for indicating
the disc data (time information, etc.).
The KY-252 board consists of the key input switches (S6 to
$29) and the SKIP operation indication LED (D360).
HA-17 Board, JK-40 Board
The AES/EBU format digital audio data input via the KC-30
board receiver (ICD1) 1s decoded by digital input IC (ICA3)
and input to the digital fitter (ICB4) ICB1 and ICB2
are PLL low pass filter and VCO for generating the clock
The digital data from which aliasing noise has been
eliminated by the digital filter (ICB4) is converted into the
analog signal by the D/A converter (ICA5) and output from the
headphone jack (J1) of the JK-40 board via the headphone
amplifier (ICB7). The headphone amplifier (ICB7) is operated
by a single power supply The commons of the control (RV1)
of the JK-40 board and the jack (J1) are not GND potentials
As to power supply for the D/A converter (ICA5) and
headphone amplifier (ICB7), the analog +5 V generated by
ICC3 ts used.