Sony CX-JTD8 - Page 79

79
CX-JTD8
Pin No. Pin Name I/O Description
189 VNW — Power supply for 5V tolerance voltage input
190 ALE O Latch enable signal output for address data demux
191 RST_SPC O Reset signal output to the mechanism controller
192 INT/EXT O Input selection signal output for SDBus or ADC (not used)
193 HCS2 O Chip select signal output for Medusa (not used)
194 HCS1 I/O Not used
195 HCS0 O Chip select signal output to the external ROM
196 VDDP — Power supply terminal (+3.3V) (I/O signal)
197 TRST I Reset signal input
198 TDO O Data output
199 TDI I Data input
200 TMS I TMS signal input
201 TCK I TCK signal input
202 RESET I ZIVA reset input
203 BUS CLK I/O Not used
204 GND — Ground terminal (inside core)
205 VDD — Power supply terminal (+1.8V) (inside core)
206 HA3 I/O Address bus 3
207 HA2 I/O Address bus 2
208 GNDP — Ground terminal (I/O signal)