81
CX-JTD8
Pin No. Pin Name I/O Description
53 XHAC I DVD mode: Serial data request signal input from ZIVA5X-C1F
54 HINT O Not used (Pull up)
55 XS16 O Not used (Pull up)
56 HA1 I Not used (Pull up)
57 XPDI I/O Not used (Pull up)
58 VDDS — Power supply (+5V)
59, 60 HA0, HA2 I Not used (Pull up)
61 VSS — Ground (open)
62, 63 HCS0, HCS1 I Not used
64 VDD — Power supply (+3.3V)
65 DASP I/O Not used
66 to 69
MDB0 to MDB3
I/O Two-way data bus with the D-RAM
70 VSS — Ground
71 MDB4 I/O Two-way data bus with the D-RAM
72 VDD5V — Power supply (+5V)
73 to 75
MDB5 to MDB7
I/O Two-way data bus with the D-RAM
76 XMWR O Write enable signal output to the D-RAM
77 VDD — Power supply (+3.3V)
78 XRAS O Row address strobe signal output to the D-RAM
79, 80 MA0, MA1 O Address signal output to the D-RAM
81 VSS — Ground
82 to 87 MA2 to MA7 O Address signal output to the D-RAM
88 VDD — Power supply (+3.3V)
89 MA8 O Address signal output to the D-RAM
90 VSS — Ground
91 MA9/MNT0 O Address signal output to the D-RAM
92 MNT1/MNT1 O EEPROM ready signal output to CXP973064
93 MNT2/MNT2 O Address signal output to the D-RAM
94 XMOE O Output enable signal output to the D-RAM
95 XCAS O Column address strobe signal output to the D-RAM
96, 97 MDB8, MDB9 I/O Two-way data bus with the D-RAM
98 VSS — Ground
99 MDBA I/O Two-way data bus with the D-RAM
100 VDD — Power supply (+3.3V)
101, 102
MDBB, MDBC
I/O Two-way data bus with the D-RAM
103 VDD5V — Power supply (+5V)
104 to 106 MDBD to MDBF
I/O Two-way data bus with the D-RAM
107 GFS O Guard frame sync signal output to CXP973064-226R
108 VSS — Ground
109 APEO O Absolute phase error signal output
110 VDD — Power supply (+3.3V)
111 DASYO O RF binary signal output
112 GNDA5 — Ground
113, 114 ASF1, AFS2 — Filter connected terminal for selection the constant asymmetry compensation
115 DASYI I Analog signal input after integrated from the RF binary signal
116 RFDCC I Input terminal for adjusting DC cut high-pass filter for RF signal
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