Sony HCD-MD5 - Page 56

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1 FS256 O 11.2896 MHz clock output (MCLK system). Not Used (Open).
2 FOK O FOK signal output to the MD system control (IC201). “H” is output when focus is on.
3 DFCT O Defect signal ON/OFF select signal output to the CXD2538CR (IC271).
4 SHCK O Track jump detect signal output to the MD system control (IC201).
5 SHCKEN I Track jump detect enable signal input. Not Used (Connected to ground).
6 WRPWR I Laser power select signal input from the MD system control (IC201).
7 DIRC I Not used (Connected to DVDD).
8 SWDT I Writing data signal input from the MD system control (IC201).
9 SCLK I Serial clock signal input from the MD system control (IC201).
10 XLAT I Serial latch signal input from the MD system control (IC201).
11 SRDT O Reading data signal output to the MD system control (IC201).
12 SENS O (3) Internal status (SENSE) output to the MD system control (IC201).
13 ADSY O ADIP sync signal output (Open)
14 SQSY O
Subcode Q sync (SCOR) output to the MD system control (IC201). “L” is output every 13.3 msec.
Almost all “H” is output.
15 DQSY O
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD system control (IC201).
“L” is output every 13.3 msec. Almost all “H” is output.
16 XRST I Reset signal input from the MD system control (IC201). When reset:’’L”.
17 TEST4 I Test pin (Connected to ground).
18 CLVSCK O Not used (Open).
19 TEST5 I Test pin (Connected to ground).
20 DOUT O Digital audio signal output (Optical output). Not Used (Open).
21 DIN I Digital audio signal input (Optical input).
22 FMCK O ADIP FM demodulation clock signal output (Open)
23 ADER O ADIP CRC flag output. “H”: Error (Open)
24 REC I
Recording/Playback select signal input from the MD system control (IC201).
Recording: “H”, Playback: “L”.
25 DVSS — GND (Digital system)
26 DOVF I Digital audio output parity flag input (Connected to ground)
27 DODT I Digital audio output 16-bit data input from the CXD2536CR (IC271).
28 DIDT O Digital audio input 16-bit data output to the CXD2536CR (IC271).
29 DTI I Recording audio data signal input from the CXD2536CR (IC271).
30 DTO O (3) Playback audio signal output to the CXD2536CR (IC271).
31 C2PO O
C2PO signal output (output indicating data error status) to the CXD2536CR (IC271).
Playback: C2PO (“H”), Digital recording: D. In Vflag, Analog recording: “L”.
32 BCK O Bit clock signal output to the CXD2536CR (IC271). (2.8224 MHz) (MCLK system)
33 LRCK O L/R clock signal output to the CXD2536CR (IC271). (44.1 KHz) (MCLK system)
34 XTAO O System clock (512Fs=22.5792 MHz) signal output
35 XTAI I System clock (512Fs=22.5792 MHz) signal input from the CXD2536CR (IC271). (Open)
36 MCLK O MCLK clock (22.5792 MHz) signal output (Open)
37 XBCK O Inverted output of Pin 32 (BCK) (Open)
38 DVDD — Power supply pin (+5V) (Digital system)
39 WDCK O WDCK clock (88.2 kHz) signal output (MCLK system) (Open)
40 RFCK O RFCK clock (7.35 kHz) signal output (MCLK system) (Open)
Pin No. Pin Name I/O Function
BD (MD) Board IC121 CXD2535BR
(Digital Signal Processing, Digital Servo Signal Processing, EFM/ACIRC Encorder/Decorder)