Sony HCD-MD5 - Page 63

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43 ABCK O Bit clock signal output to the A/D, D/A converter (IC303).
44 ALRCK O L/R clock signal output to the A/D, D/A converter (IC303).
45 SA2 O Address signal output. Not used (Open).
46 SA1 O
47 SA0 O
Address signal output. Not used (Open).
48 A11 O
49 A10 O
50 VSS — Ground
51 VDD — Power supply (+5V)
52 A03 O
53 A02 O
54 A01 O
55 A00 O
56 A04 O Address signal output to the RAM (IC272).
57 A05 O
58 A06 O
59 A07 O
60 A08 O
61 XOE O Output enable control signal output to the RAM (IC272).
62 XCAS O Column address strobe signal output to the RAM (IC272).
63 VSS — Ground
64 XCS O Chip select signal output to the RAM (IC272). Not used (Open).
65 A09 O Address signal output to the RAM (IC272).
66 XRAS O Low address strobe signal output to the RAM (IC272).
67 XWE O Reading/Writing control signal output to the RAM (IC272).
68 D1 I/O
69 D0 I/O
Data signal input/output with the RAM (IC272).
70 D2 I/O
71 D3 I/O
72 D4 I/O
73 D5 I/O Data signal input/output. Not used (Open).
74 D6 I/O
75 VSS — Ground
76 D7 I/O Data signal input/output. Not used (Open).
77 ERR I/O Error (C2PO) data input/output to an external RAM. Not used (Open).
78 EXTC2R I External RAM select input for error data writing (“H”:External RAM) (Fixed at “L”)
79 BUSY O BUSY signal output for RAM access. Not used (Open).
80 EMP O Immediately before EMPTY or FULL of ATRAC data (When DSC=ASC+1:“H”). Not used (Open).
81 FUL O Immediately before FULL or EMPTY of ATRAC data (When ASC=DSC+1:“H”). Not used (Open).
82 EQL O EMPTY of ATRAC data (When DSC=ASC:“H”) (Open)
83 MDLK O Main/Sub of recording/playback data (“H”:Sub linking, “L”:Main.) (Open)
84 CPSY O Interpolation sync signal output (Open)
85 CTMD0 O
DSC counter mode output (Open)
86 CTMD1 O
87 SPO O System clock (512Fs=22.5792 MHz) signal output to the CXD2535BR (IC121).
Pin No. Pin Name I/O Function