Sony LBT-A57CD - Section 5 Diagrams (TC-D507); 5-1. Circuit Boards Location; 5-2. Semiconductor Lead Layouts

2. Mode : playback
gesaises viv
ce oun [ONSOM
UNE OLT | Fin@-Lch
pin@:Reh.
Playback the signal recorded in step 1.
Confirm that the 10kHz playback output is 0+0.5dB relative
to the 315Hz output. If necessary, adjust RV12 (L-CH), RV22
(R-CH) and repeat the steps given above.
Adjustment Location : MD-B board
Record Level Adjustment ‘DECK B]
Setting :
REC LEVEL control : Standard Record (See page 7).
Procedure :
1. Mode: record
AF OSC
Unrecord tape
Jorn CS-123
oto a
{1000 set
one
es
600.2,
LINE 1N
CN504 315H2z, 63mV (~1.8dB)
pin@:Lch
pin@: Reh,
2. Mode: playback
recorded
portion
Sak
LINE OUT [rn ]
pin@):Reh,
3. Playback the signal recorded in step 1.
Confirm that the signal level is within the adjustment limits
below. If necessary, adjust RV101 (L-CH), RV201 (R-CH)
and repeat the step 1-2.
Adjustment Limits : —3.8dB+0.5dB (0.47—0.53V)
Adjustment Location : MAIN board (component side)
— Adjustment Parts Location Diagrams —
hie ecw} ECORD BIAS Adj
DECK B ——avi2 cu) * BIAS Saearent
DECK A
La
S |AV72 (HIGH) | TAPE SPEED
}——AV71 NORMAL) }. Adiustment
ie RV27 (RCH) | pLayBACK LEVEL
o+ vit (-cu) ) Adiustment
|Y
MD-B Board
|
\__RV72 (HIGH) ) Tape SPEED
v71 (worMat) J Adustment
@
ae
Adjustment
LEE pe PLAYBACK LEVEL
RVIT (L-CH)
MD-A Board
MAIN BOARD (COMPONENT SIDE)
O--AV101 L-CH RECORD
LEVEL Adjustment
O-RVv201 R-CH RECORD[
LEVEL Adjustment)
cCN504
cr
SECTION 5
DIAGRAMS
5-1. CIRCUIT BOARDS LOCATION
MD-A board
2 SW-B board
Le
SW-A board
PANEL board
CONTROL (B) board
5-2. SEMICONDUCTOR LEAD LAYOUTS
TA7272P 28B1013-4 DTC144ES
i
Et ry
2$B1094-LK
1
oe a
DTA114ES Ry)
DTA144ES ~
DTC143TS ll 1N4148M
Ri W 10E2N
HZS6A1N
UZL-7L2
- cathode
anode
SEL2210S-C
SEL2410E-D
SEL2910A-C
ce cathode
tong short
€
cy
anode
—10—
onode cathode