Sony MCS-8M - Page 132

MIX-54 (13/42)
0.1uF
C1402
0.8 CL1403
100
R1402
0.1uF
C1400
0.1uF
C1412
22 R1404
22 R1407
0.8 CL1400
0.1uF
C1414
22 R1405
GND
22 R1406
0.8
CL1402
0
R1400
NM
0.1uF
C1401
+1.8
V
0.1uF
C1403
10k R1414
0.1uF
C1405
0
R1412
0.1uF
C1404
+1.8V
10k R1415
0.1uF
C1411
+1.8
V
22 R1411
0.8 CL1405
0.1uF
C1406
22 R1408
0
R1413
100
R1403
0.1uF
C1410
+1.8V
0.1uF
C1408
0.1uF
C1413
22 R1410
0.8
CL1404
0.8 CL1401
0.1uF
C1415
0
R1401
NM
0.1uF
C1407
0.1uF
C1409
22 R1409
GND
MT46H16M32LFB5-6IT:C
IC1400
VSS:1
A1
VDDQ:2
B1
VSSQ:3
C1
VDDQ:4
D1
VSSQ:4
E1
VDD:2
F1
CKE
G1
A9
H1
A6
J1
A4
K1
VSSQ:5
L1
VDDQ:7
M1
VSSQ:7
N1
VDDQ:9
P1
VSS:3
R1
DQ15
R2
VSSQ:9
R3
VDDQ:10
R7
DQ0
R8
VDD:3
R9
VSSQ:8
P9
VDDQ:8
N9
VSSQ:6
M9
VDDQ:6
L9
A3
K9
A1
J9
BA1
H9
RAS
G9
VSS:2
F9
VDDQ:5
E9
TEST
D9
VDDQ:3
C9
VSSQ:2
B9
VDD:1
A9
DQ16
A8
VDDQ:1
A7
VSSQ:1
A3
DQ31
A2
DQ29
B2
DQ27
C2
DQ25
D2
DQS3
E2
DM3
F2
CK
G2
A11
H2
A7
J2
DM1
K2
DQS1
L2
DQ9
M2
DQ11
N2
DQ13
P2
DQ14
P3
DQ1
P7
DQ2
P8
DQ4
N8
DQ6
M8
DQS0
L8
DM0
K8
A0
J8
BA0
H8
CAS
G8
DM2
F8
DQS2
E8
DQ22
D8
DQ20
C8
DQ18
B8
DQ17
B7
DQ30
B3
DQ28
C3
DQ26
D3
DQ24
E3
NC
F3
CK
G3
A12
H3
A8
J3
A5
K3
DQ8
L3
DQ10
M3
DQ12
N3
DQ3
N7
DQ5
M7
DQ7
L7
A2
K7
A10/AP
J7
CS
H7
WE
G7
A13
F7
DQ23
E7
DQ21
D7
DQ19
C7
MT46H16M32LFB5-6IT:C
IC1401
VSS:1
A1
VDDQ:2
B1
VSSQ:3
C1
VDDQ:4
D1
VSSQ:4
E1
VDD:2
F1
CKE
G1
A9
H1
A6
J1
A4
K1
VSSQ:5
L1
VDDQ:7
M1
VSSQ:7
N1
VDDQ:9
P1
VSS:3
R1
DQ15
R2
VSSQ:9
R3
VDDQ:10
R7
DQ0
R8
VDD:3
R9
VSSQ:8
P9
VDDQ:8
N9
VSSQ:6
M9
VDDQ:6
L9
A3
K9
A1
J9
BA1
H9
RAS
G9
VSS:2
F9
VDDQ:5
E9
TEST
D9
VDDQ:3
C9
VSSQ:2
B9
VDD:1
A9
DQ16
A8
VDDQ:1
A7
VSSQ:1
A3
DQ31
A2
DQ29
B2
DQ27
C2
DQ25
D2
DQS3
E2
DM3
F2
CK
G2
A11
H2
A7
J2
DM1
K2
DQS1
L2
DQ9
M2
DQ11
N2
DQ13
P2
DQ14
P3
DQ1
P7
DQ2
P8
DQ4
N8
DQ6
M8
DQS0
L8
DM0
K8
A0
J8
BA0
H8
CAS
G8
DM2
F8
DQS2
E8
DQ22
D8
DQ20
C8
DQ18
B8
DQ17
B7
DQ30
B3
DQ28
C3
DQ26
D3
DQ24
E3
NC
F3
CK
G3
A12
H3
A8
J3
A5
K3
DQ8
L3
DQ10
M3
DQ12
N3
DQ3
N7
DQ5
M7
DQ7
L7
A2
K7
A10/AP
J7
CS
H7
WE
G7
A13
F7
DQ23
E7
DQ21
D7
DQ19
C7
CXD9219GG
IC6
(7/9)
BM2DT00
L27
BM2DT01
M29
BM2DT02
L26
BM2DT03
L29
BM2DT04
K27
BM2DT05
L28
BM2DT06
J27
BM2DT07
K29
BM2DT08
J25
BM2DT09
G29
BM2DT10
H26
BM2DT11
H28
BM2DT12
H27
BM2DT13
H29
BM2DT14
J26
BM2DT15
J29
BM2DT16
A20
BM2DT17
B20
BM2DT18
C20
BM2DT19
A21
BM2DT20
D21
BM2DT21
A22
BM2DT22
C21
BM2DT23
C22
BM2DT24
E22
BM2DT25
B25
BM2DT26
D22
BM2DT27
A25
BM2DT28
E21
BM2DT29
A24
BM2DT30
A23
BM2DT31
B23
BM2DQS0
K28
BM2DQS1
G28
BM2DQS2
B22
BM2DQS3
A26
OM2AD00
D29
OM2AD01
D28
OM2AD02
G25
OM2AD03
H25
OM2AD04
F29
OM2AD05
F27
OM2AD06
F26
OM2AD07
F25
OM2AD08
E24
OM2AD09
D25
OM2AD10
B26
OM2AD11
C25
OM2AD12
D24
OM2AD13
C24
OM2ADB0
H24
OM2ADB1
G27
OM2CASX
E23
OM2CKE
E27
OM2CSX
G24
OM2DM0
L25
OM2DM1
J24
OM2DM2
E20
OM2DM3
F22
OM2RASX
C23
OM2WEX
F23
OM2CLK
E28
OM2CLKX
E29
CXD9219GG
IC6
(6/9)
BM1DT00
AJ21
BM1DT01
AJ22
BM1DT02
AG20
BM1DT03
AH22
BM1DT04
AG21
BM1DT05
AJ23
BM1DT06
AF21
BM1DT07
AH23
BM1DT08
AG25
BM1DT09
AG23
BM1DT10
AG24
BM1DT11
AJ26
BM1DT12
AF22
BM1DT13
AH25
BM1DT14
AG22
BM1DT15
AJ25
BM1DT16
V27
BM1DT17
W29
BM1DT18
W27
BM1DT19
W28
BM1DT20
W26
BM1DT21
Y29
BM1DT22
Y27
BM1DT23
Y28
BM1DT24
AC27
BM1DT25
AA25
BM1DT26
AA26
BM1DT27
AC29
BM1DT28
AA27
BM1DT29
AB28
BM1DT30
Y25
BM1DT31
AB29
BM1DQS0
AJ24
BM1DQS1
AH26
BM1DQS2
AA29
BM1DQS3
AD29
OM1AD00
AC25
OM1AD01
AB25
OM1AD02
AE23
OM1AD03
AE22
OM1AD04
AF25
OM1AD05
AE24
OM1AD06
AF28
OM1AD07
AG26
OM1AD08
AD26
OM1AD09
AF29
OM1AD10
AB27
OM1AD11
AE26
OM1AD12
AD27
OM1AD13
AC28
OM1ADB0
AD24
OM1ADB1
AD22
OM1CASX
AB24
OM1CKE
AE27
OM1CSX
AD23
OM1DM0
AE21
OM1DM1
AF24
OM1DM2
V26
OM1DM3
AA24
OM1RASX
AB26
OM1WEX
AC24
OM1CLK
AE28
OM1CLKX
AE29
PPK1_DDR_D[8]
PPK1_DDR_D[17]
PPK1_DDR_A[4]
PPK1_DDR_D[11]
PPK1_DDR_D[9]
PPK1_DDR_D[24]
PPK1_DDR_D[3]
PPK1_DDR_D[22]
PPK1_DDR_D[20]
PPK1_DDR_S3
PPK1_DDR_D[29]
PPK1_DDR_D[3]
PPK1_OMCSX
PPK1_DDR_D[26]
PPK1_OMRSX
PPK1_DDR_D[18]
PPK1_DDR_D[18]
PPK1_DDR_A[6]
PPK1_DDR_S2
PPK1_OMCEX
PPK1_DDR_S2
PPK1_OMCKE
PPK1_DDR_D[25]
PPK1_DDR_D[30]
PPK1_DDR_D[13]
PPK1_DDR_A[3]
PPK1_DDR_D[8]
PPK1_DDR_M0
PPK1_DDR_D[20]
PPK1_DDR_A[6]
PPK1_DDR_D[0-31]PPK1_DDR_D[0-31]
PPK1_DDR_D[23]
PPK1_DDR_D[9]
PPK1_DDR_D[7]
PPK1_DDR_M1
PPK1_OMCKE
PPK1_DDR_A[0]
PPK1_DDR_A[5]
PPK1_OMCLKX
PPK1_DDR_A[11]
PPK1_DDR_D[31]
PPK1_DDR_A[3]
PPK1_DDR_D[28]
PPK1_OMCSX
PPK1_DDR_D[4]
PPK1_DDR_B0
PPK1_DDR_D[14]
PPK1_DDR_A[7]
PPK1_DDR_D[2]
PPK1_DDR_D[24]
PPK1_DDR_S1
PPK1_OMCLK
PPK1_DDR_D[19]
PPK1_DDR_A[11]
PPK1_DDR_A[8]
PPK1_DDR_M3
PPK1_DDR_D[1] PPK1_OMCLK
PPK1_DDR_D[13]
PPK1_DDR_A[0-13]
PPK1_DDR_D[5]
PPK1_DDR_D[27]
PPK1_DDR_A[10]
PPK1_DDR_D[31]
PPK1_DDR_D[0]
PPK1_DDR_D[17]
PPK1_OMCLKX
PPK1_DDR_D[11]
PPK1_DDR_D[16]
PPK1_DDR_A[9]
PPK1_DDR_A[0-13] PPK1_DDR_A[0-13]
PPK1_DDR_D[10]
PPK1_DDR_D[28]
PPK1_DDR_S0
PPK1_DDR_D[25]
PPK1_DDR_M2
PPK1_DDR_D[12]
PPK1_DDR_D[6]
PPK1_DDR_D[22]
PPK1_DDR_S1
PPK1_DDR_A[12]
PPK1_DDR_D[5]
PPK1_DDR_A[13]
PPK1_DDR_S0
PPK1_DDR_D[1]
PPK1_DDR_D[15]
PPK1_DDR_A[1]
PPK1_DDR_S3
PPK1_DDR_D[21]
PPK1_DDR_D[19]
PPK1_DDR_A[1]
PPK1_OMWEX
PPK1_DDR_D[21]
PPK1_DDR_D[14]
PPK1_DDR_A[7]
PPK1_DDR_D[10]
PPK1_DDR_D[27]
PPK1_OMCEX
PPK1_DDR_A[4]
PPK1_DDR_D[6]
PPK1_DDR_D[15]
PPK1_DDR_D[7]
PPK1_DDR_M3
PPK1_DDR_D[29]
PPK1_DDR_A[9]
PPK1_DDR_D[30]
PPK1_DDR_D[2]
PPK1_DDR_M1
PPK1_DDR_D[26]
PPK1_DDR_D[16]
PPK1_OMWEX
PPK1_DDR_D[23]
PPK1_DDR_D[12]
PPK1_DDR_D[4]
PPK1_DDR_D[0-31]
PPK1_DDR_A[2]
PPK1_DDR_M0
PPK1_DDR_A[0]
PPK1_DDR_M2
PPK1_DDR_D[0]
PPK1_DDR_B1
PPK1_OMRSX
PPK2_DDR_A[12]
PPK2_DDR_D[21]
PPK2_DDR_D[2]
PPK2_DDR_D[9]
PPK2_DDR_A[0-13] PPK2_DDR_A[0-13]
PPK2_DDR_A[5]
PPK2_DDR_S3
PPK2_DDR_A[7]
PPK2_DDR_M0
PPK2_DDR_D[23]
PPK2_DDR_A[9]
PPK2_DDR_A[4]
PPK2_DDR_D[24]
PPK2_DDR_A[1]
PPK2_DDR_D[14]
PPK2_DDR_A[2]
PPK2_DDR_D[16] PPK2_DDR_D[25]
PPK2_DDR_A[3]
PPK2_DDR_D[8]
PPK2_OMCEX
PPK2_DDR_D[13]
PPK2_DDR_D[11]
PPK2_DDR_A[10] PPK2_DDR_A[13]
PPK2_DDR_B0
PPK2_DDR_D[15]
PPK2_OMCLKX
PPK2_DDR_D[27]
PPK2_DDR_S3
PPK2_DDR_D[3]
PPK2_DDR_D[0-31]PPK2_DDR_D[0-31]
PPK2_DDR_D[3]
PPK2_DDR_D[1]
PPK2_DDR_D[17]
PPK2_DDR_D[10]
PPK2_DDR_D[29]
PPK2_DDR_D[22]
PPK2_DDR_D[4]
PPK2_DDR_D[20]
PPK2_DDR_A[6]
PPK2_DDR_D[9]
PPK2_DDR_S0
PPK2_DDR_A[8]
PPK2_DDR_A[7]
PPK2_OMCSX
PPK2_DDR_A[13]
PPK2_DDR_D[0]
PPK2_DDR_D[14]
PPK2_DDR_D[28]
PPK2_DDR_D[20]
PPK2_DDR_D[0-31]
PPK2_DDR_D[5]
PPK2_DDR_D[31]
PPK2_DDR_A[3]
PPK2_DDR_D[4]
PPK2_DDR_A[12]
PPK2_DDR_A[10]
PPK2_DDR_D[31]
PPK2_DDR_D[0]
PPK2_DDR_D[12]
PPK2_DDR_M2
PPK2_DDR_S1
PPK2_DDR_D[27]
PPK2_DDR_D[21]
PPK2_DDR_A[0]
PPK2_DDR_D[22]
PPK2_OMWEX
PPK2_OMCSX
PPK2_DDR_A[6]
PPK2_DDR_D[23]
PPK2_DDR_D[18]
PPK2_DDR_D[18]
PPK2_DDR_D[11]
PPK2_DDR_D[5]
PPK2_OMRSX
PPK2_DDR_D[6]
PPK2_OMWEX PPK2_DDR_D[26]
PPK2_DDR_A[1]
PPK2_DDR_A[0-13]
PPK2_DDR_D[12]
PPK2_DDR_D[16]
PPK2_DDR_D[13]
PPK2_DDR_M0
PPK2_DDR_M2
PPK2_DDR_D[26]
PPK2_OMCLK
PPK2_DDR_D[25]
PPK2_DDR_M1
PPK2_DDR_B1
PPK2_DDR_A[11]
PPK2_DDR_D[1]
PPK2_DDR_S0
PPK2_DDR_D[2]
PPK2_DDR_D[28]
PPK2_DDR_D[30]
PPK2_OMCLKX
PPK2_DDR_D[10]
PPK2_DDR_A[2]
PPK2_DDR_M3
PPK2_DDR_A[5]
PPK2_DDR_A[8]
PPK2_DDR_D[17]
PPK2_DDR_D[8]
PPK2_DDR_A[4]
PPK2_DDR_A[9]
PPK2_OMCEX
PPK2_DDR_A[11]
PPK2_DDR_S2
PPK2_DDR_S2
PPK2_OMCKE
PPK2_DDR_A[0]
PPK2_DDR_D[29]
PPK2_DDR_D[30]
PPK2_DDR_D[19]
PPK2_OMCKE
PPK2_OMRSX
PPK2_DDR_M3
PPK2_DDR_M1
PPK2_OMCLK
PPK2_DDR_D[7]
PPK2_DDR_D[15]
PPK2_DDR_S1
PPK2_DDR_D[6]
PPK2_DDR_D[19]
PPK2_DDR_D[24]
PPK2_DDR_D[7]
PPK1_DDR_B1
PPK1_DDR_B0
PPK2_DDR_B1
PPK2_DDR_B0
PPK2_DDR_D[0-31] PPK2_DDR_A[0-13] PPK1_DDR_A[0-13]
PPK1_DDR_D[0-31]
PPK1_DDR_A[12]
PPK1_DDR_A[8] PPK1_DDR_A[5]
PPK1_DDR_A[13] PPK1_DDR_A[10]
PPK1_DDR_A[2]
MIX-54 (13/42)
BOARD NO. 1-884-046-13
MCS-8M_MIX-54_005_13
MCS-8M
4-28