45
STR-DB870/DB1070
• DIGITAL BOARD IC1501 CDX9617R (AUDIO DSP1)
Pin No. Pin Name I/O Description
1
VSS —
Ground terminal
2 XRST I
Reset signal input from the system controller (IC1703)
3 EXTIN I
Master clock input terminal Not used (fixed at “L”)
4 FS2 I
Sampling frequency select signal input terminal Not used (fixed at “L”)
5 VDDI —
Power supply terminal (+2.5V)
6 FS1 I
Sampling frequency select signal input terminal Not used (fixed at “L”)
7 PLOCK O
Internal PLL lock signal output terminal Not used (open)
8 VSS —
Ground terminal
9 MCLK1 I
Systen clock input terminal (13.5MHz)
10 VDDI —
Power supply terminal (+2.5V)
11 VSS —
Ground terminal
12 MCLK2 O
Systen clock output terminal (13.5MHz)
13 MS I
Master/slave active select terminal “L”: internal clock, “H”: external clock
14
SCKOUT O
Internal system clock output terminal Not used (open)
15
LRCKI1 I
L/R sampling clock signal input from the audio interface receiver (IC1408)
16
VDDE —
Power supply terminal (+3.3V)
17 BCKI1 I
Bit clock signal input from the audio interface receiver (IC1408)
18 SDI1 I
Audio data input from the A/D converter (IC1503)
19 LRCKO O
L/R sampling clock signal output to the audio DSP2 (IC1601)
20 BCKO O
Bit clock signal output to the audio DSP2 (IC1601)
21
VSS —
Ground terminal
22
KFSIO I/O
Audio clock signal (384fs/256fs) in/out terminal
23 to 26
SDO1 to SDO4 O
Audio serial data output to the audio DSP2 (IC1601)
27 SPDIF O
S/PDIF output terminal Not used (open)
28 LRCKI2 I
L/R sampling clock signal input from the audio interface receiver (IC1408)
29
BCKI2 I
Bit clock signal input from the audio interface receiver (IC1408)
30
SDI2 I
Audio serial data input from the audio interface receiver (IC1408)
31
VSS —
Ground terminal
32
HACN O
Host acknowledge signal output to the system controller (IC1703)
33
HDIN I
Host serial data input from the system contrller (IC1703)
34
HCLK I
Host clock signal input from the system contrller (IC1703)
35
HDOUT O
Host serial data output to the system contrller (IC1703)
36
HCS I
Host chip select input from the system contrller (IC1703)
37
SDCLK O
SD-RAM clock output terminal Not used (open)
38
CLKEN O
SD-RAM clock enable output terminal Not used (open)
39
RAS O
Row address strobe signal output terminal Not used (open)
40
VDDI —
Power supply terminal (+2.5V)
41
VSS —
Ground terminal
42
CAS O
Column address strobe signal output terminal Not used (open)
43
DQM/OE0 O
Mask data output terminal
44
CS0 O
Chip select isignal output to the S-RAM (IC1502)
45
WE0 O
Write enable signal output to the S-RAM (IC1502)
46
VDDE —
Power supply terminal (+3.3V)
47
WMD1 I
External memory wait mode setting terminal (fixed at “H”)
48
VSS —
Ground terminal
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