47
STR-DB870/DB1070
• DIGITAL BOARD IC1601 CXD9616R (AUDIO DSP2)
Pin No. Pin Name I/O Description
1
VDDI —
Power supply terminal (+2.5V)
2
EXTIN I
Not used (fixed at “L”)
3, 4
WMD1, WMD0 I
External memory wait mode setting terminal (fixed at “H”)
5 MOD1 I
Mode select signal input terminal “L”: 384fs, “H”: 256fs
6
MOD0 I
Mode select signal input terminal “L”: single chip mode, “H”: can not use
7
VSS —
Ground terminal
8 XRST I
Reset signal input from the system controller (IC1703)
9
VSS —
Ground terminal
10
SCKOUT O
Serial clock signal output to the D/A converter (IC1201, 1202)
11
VDDI (PLL) —
Power supply terminal (+2.5V) (for PLL)
12
SYNC I
Sync/unsync select signal input terminal “L”: sync
13 to 15
PAGE2 to PAGE0
O
External memory page select signal output terminal Not used (open)
16 PLOCK O
Internal PLL lock signal output teminal Not used (open)
17
BTACK I
Boot mode display signal output teminal Not used (open)
18
VDDE —
Power supply terminal (+3.3V)
19
VSS —
Ground terminal
20 to 22
D31 to D29 I/O
Two-way data bus with the S-RAM (IC1602)
23 A17 O
Address signal output terminal Not used (open)
24
VSS —
Ground terminal
25
SDO3 O
Audio serial data output to the D/A converter (IC1201)
26
SDO4 O
Audio serial data output to the D/A converter (IC1202)
27, 28
SDI1, SDI2 I
Audio serial data input from the audio DSP1 (IC1501)
29
LRCKI1 I
L/R sampling clock signal input from the audio DSP1 (IC1501)
30
VSS —
Ground terminal
31, 32
D28, D27 I/O
Two-way data bus with the S-RAM (IC1602)
33
A16 O
Address signal output terminal Not used (open)
34
A15 O
Address signal output to the S-RAM (IC1602)
35
SDI3 I
Audio serial date input from the audio DSP1 (IC1501)
36
L2 —
Not used (open)
37
VDDI —
Power supply terminal (+2.5V)
38
BCKI1 I
Bit clock signal input from the audio DSP1 (IC1501)
39
SDI4 I
Audio serial data input from the audio DSP1 (IC1501)
40
MS I
Master/slave active select terminal “L”: internal clock, “H”: external clock (fixed at “L”)
41, 42
A14, A13 O
Address signal output to the S-RAM (IC1602)
43, 44
D26, D25 I/O
Two-way data bus with the S-RAM (IC1602)
45
VSS —
Ground terminal
46
BCKI2 I
Bit clock signal input terminal Not used (open)
47, 48
FS2, FS1 I
Sampling frequency select signal input terminal Not used (open)
49
SPDIF I
S/PDIF output terminal Not used (open)
50
A12 O
Address signal output to the S-RAM (IC1602)
51 to 53
D24 to D22 I/O
Two-way data bus with the S-RAM (IC1602)
54
VDDE —
Power supply terminal (+3.3V)
55
VSS —
Ground terminal
56 to 58
D21 to D19 I/O
Two-way data bus with the S-RAM (IC1602)
59
A11 O
Address signal output to the S-RAM (IC1602)
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