7-14
BVM-A14
7-14
BC (2/3)BC (2/3)
29
28
1
9
24
OUT1-U
STBY1
10
5
1
STBY2
VCC
LL1
OUT1-D
INV1
Q351
L350
F351
DD-CONV
SW
DD-CONV
SW
DD-CONV
SW
DD-CONV
SW
OVER CURRENT
DETECT
4.0V
RESET
LED
DRIVE
27
Q353
Q363
Q358,364-366
Q367
IC350
IC404
DC/DC CONVERTER
F352
L352
TP351
17
18
15
OUT2-U
LL2
OUT2-D
INV2
Q356
L351
F350
+1.8V
+3.3V
19
Q354
L354
L353
TP350
+5V
Q362
Q360
BC (2/3)
D361
12V
REG
IC352
TP354
TP302
+12V+15V
1.5V
REG
IC351
+1.5V+3.3V
CN153
REMOTE2
REM [0]
REM [5]
REM [1]
REM [6]
REM [2]
REM [7]
REM [3]
REM [4]
REM [0]-[7]
1
2
3
4
5
6
7
8
9
8
8
8
IC303
24
1,3,5,9,11,13
2,4,6,8,10,12
D014
7 SEG LED
2
4
IC301
FPGA ROM
DATA
DCLK
NCONFIG
NSTATUS
CONF DONE
H2
K4
H3
J13
K13
2
3
13
8
9
19
3
11
1
DATA
DCLK
nINIT CONF
OE
nCS
TMS
TCK
TDI
TDO
TMS
TCK
TDI
TDO
REM X[0]-X[7]
J15
J14
H14
H15
R11,P10,N10,P11
P12,N12,P13,P14
3/3
3/3
3/3
JATG. TMS
JATG. TCK
FPGA ROM. TDI
3/3
JATG. TDO
1/3
1/3
1/3
STATUS1
STATUS0
LED. LAN CNTRL
CONF DONE X
IC300
FPGA
IC013
D011 STATUS1
D012 STATUS2
D013 LAN CNTRL
D014 FPGA CONFIG
15
14
13
12
A1
RESET1
R2
P5
4
5
6
7
Q1
H/W. RST
H/W. RST EN
LED DRIVE
IC013
18-16
DIG1-3
2,4,5
1-3
H12,K12,L12
K5,L5,M5,M6
N6,M7,M8,M9
DIG[0]-[2]
SEG[0]-[7]
LED DRIVE
IC1011
18-11
D.P
a-g
1,3,6-11
1-8
LED DRIVE
3
8
3
7
4
8
A0-A25
A0-A25
1/3,3/3
A0
|
A25
B2,D5,A2,C5,B3,C6
B4,C7,A4,C8,B5,D8,B6,D9,A6,C9,B7
C10,B8,D10,A8,C11,A9,C12,B9,D12
LAN. A0-A3
LAN. A0 - LAN. A3
1/3
LAN. A0
|
LAN. A3
T8,R8,R7,T6
D0-D31
D0-D31
1/3,3/3
D0
|
D31
N2,P3,N1,N4,M2,N3,M1,M4,L2,L4
L1,L3,K2,K3,K1,G3,J1,G4,G2,F3,F1
F4,F2,E3,E1,E4,D1,D3,D2,C3,C2,C4
IRQ[1]-[7]
SUB
XILINX. DOE X[0]
XILINX. DOE X[1]
FREE[0]
FREE[1]
FREE[2]
VMS. ADOE X
FPGA. RESET
CS2 VMBUS X
SLOT X[2]
INIT DONE X
L15,M16,M15
N16,N15,R16,P15
F14
LG13,G14,H13,K14
L14,L13,M14,M13
E15,E16,F15,F16
G15,J16,K16,K15
ADIN X[0]
|
ADIN X[7]
ADOUT0
|
ADOUT7
POWER
STAND BY
OVERLOAD
TALLY
F12,E12,E11,D11
IRQ[1]-[7]
SUB
XILINX. DOE X[0]
XILINX. DOE X[1]
FREE[0]
FREE[1]
FREE[2]
VMS. ADOE X
FPGA. RESET
CS2 VMBUS X
SLOT X[2]
INIT DONE X
3/3
3/3
3/3
3/3
3/3
3/3
3/3
3/3
3/3
3/3
3/3
3/3
POWER
STAND BY
OVERLOAD
TALLY
3/3
3/3
3
8
4
TA A X/D
TA R/W X
TA CLK RW
N14,N13,G16
R14
R13
M12
M11
N11
T15
F13
B16
R15
D4
3/3
2
HS X[0]
VS X[0]
D7,B11
HS X[0]
VS X[0]
3/3
2
HS X[1]
VS X[1]
M3,E2
HS X[1]
VS X[1]
WAIT
RD/WR
WE0-WE3
RD
BS
IRQ4 X
BREQ
BACK
CS2
CS5
LED. DIGIT[0]
LED. DIGIT[1]
LED. WE X
LED. SEG[0]-[7]
FLASH1. RY/BY
FLASH1. WP/ACC
FLASH2. RY/BY
FLASH2. WP/ACC
CS0
CS2 FRAM X
LAN. AEN
LAN. RD
LAN. WR
LAN. ARDY
LAN. BE0
LAN. BE1
CS2 UART X
WAIT
RD/WR
WE0-WE3
RD
BS
IRQ4 X
BREQ
BACK
CS2
CS5
LED. DIGIT[0]
LED. DIGIT[1]
LED. WE X
LED. SEG[0]-[7]
FLASH1. RY/BY
FLASH1. WP/ACC
FLASH2. RY/BY
FLASH2. WP/ACC
CS0
CS2 FRAM X
LAN. AEN
LAN. RD
LAN. WR
LAN. ARDY
LAN. BE0
LAN. BE1
CS2 UART X
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
B15
A15
B12,A13,B13,B14
A11
B10
B1
E13
D14
C14
D13
H5
G5
G1
E10,E9,E8,E7,D6,E6,E5,F5
T2
R3
P4
N5
C13
P2
T4
R5
R6
R10
T13
R12
R1
TA A X/D
TA R/W X
TA CLK RW
CLK3
FPGA. CKIO
1/3
H16
ADIN X[0]-X[7]
3/3
ADOUT0-7
3/3
+5V
DELAY
+5V
Q382,383
RY301
TP352
CN350
DC OUT
5V1
CN351
5V1
IC167,166
RECEIVE BUFFER
IC311
SCHMITT
INVERTER
IC302
SCHMITT
INVERTER
IC312
OPEN
DRAIN
INVERTER
IC313
MULTIVIBRATOR
HARDWARE RESET
H/W. RESET
1/3
1/3
RESET
+3.3V
IC310
6
T9
+3.3V-3
4
3
CONF DONE X
BUS INTERFACE
24 24