DocID028599 Rev 7 57/82
UM1974 Hardware layout and configuration
81
CN7
19 D25 SPI_B_MISO PB4 I2S_3 / SPI3 -
2 D15 I2C_A_SCL PB8 I2C1_SCL
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4 D14 I2C_A_SDA PB9 I2C1_SDA
6 AREF AREF
-
AVDD/VREF+
8 GND GND ground
10 D13 SPI_A_SCK PA5 SPI1_SCK
12 D12 SPI_A_MISO PA6 SPI1_MISO
14 D11
SPI_A_MOSI/
TIM_E_PWM1
PA7
(1)(2)
or PB5
(1)
SPI1_MOSI/
TIM14_CH1
16 D10
SPI_A_CS/
TIM_B_PWM3
PD14
SPI1_CS/
TIM4_CH3
18 D9 TIMER_B_PWM2 PD15 TIM4_CH4
20 D8 I/O PF12 -
CN10
1 AVDD AVDD
-
Analog VDD
-
3 AGND AGND Analog ground
5 GND GND ground
7 A6 ADC_A_IN PB1 ADC12_IN9
9 A7 ADC_B_IN PC2 ADC123_IN12
11 A8 ADC_C_IN PF4 ADC3_IN14
13 D26 I/O PB6
I/O
15 D27 I/O PB2
17 GND GND - ground
19 D28 I/O PD13
I/O
21 D29 I/O PD12
23 D30 I/O PD11
25 D31 I/O PE2
(3)
27 GND GND - ground
29 D32 TIMER_C_PWM1 PA0 TIM2_CH1
31 D33 TIMER_D_PWM1 PB0 TIM3_CH3
33 D34 TIMER_B_ETR PE0 TIM4_ETR
2 D7 I/O PF13 -
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Table 17. NUCLEO-F429ZI and NUCLEO-F439ZI pin assignments (continued)
Connector Pin
Pin
name
Signal name
STM32
pin
Function Remark
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