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ST STM32F405 Series User Manual
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AN4488 Rev 7
1
1/50
AN4488
Power supplies
49
Figure 3.
Power supply sche
me
for STM32F469xx/F479
xx
1.
Optional. If a separate, external refere
nce voltage is connected on V
REF+
, the two capacitors (100 nF and
1 µF) must be co
nnected.
2.
V
REF+
is either connected to V
REF+
or to V
DDA
(depending on package).
3.
V
REF-
is either connected to V
REF-
or to V
SSA
(depending on package).
4.
Refer to datasheet for BYPASS_REG and PDR_ON pins connection.
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Table of Contents
Default Chapter
2
Table of Contents
2
1 Reference Documents
6
Table 2. Referenced Documents
6
2 Power Supplies
7
Digital Supply
7
Voltage Regulator
7
Regulator off Mode
7
Figure 1. BYPASS_REG Supervisor Reset Connection
8
Power Supply Schemes
9
Figure 2. Power Supply Scheme (Excluding Stm32F469Xx/F479Xx)
10
Figure 3. Power Supply Scheme for Stm32F469Xx/F479Xx
11
Analog Supply
12
3 Reset and Power Supply Supervisor
13
System Reset
13
NRST Circuitry Example
13
Figure 4. Reset Circuit
13
Figure 5. NRST Circuitry Example
14
Stm32F412Xx, Stm32F413Xx, Stm32F423Xx, Stm32F446Xx, Stm32F469Xx
14
And Stm32F479Xx)
14
Power Supply Supervisor
15
PDR_ON Circuitry Example
15
Figure 6. NRST Circuitry Timings Example
15
Stm32F411Xx, Stm32F412Xx, Stm32F413Xx, Stm32F423Xx, Stm32F446Xx
15
Stm32F469Xx and Stm32F479Xx)
15
Figure 7. PDR_ON Simple Circuitry Example
16
Stm32F411Xx, Stm32F413Xx, Stm32F423Xx, Stm32F412Xx, Stm32F446Xx
16
Power on Reset (POR) / Power down Reset (PDR)
17
Figure 8. PDR_ON Timings Example
17
Programmable Voltage Detector (PVD)
18
Figure 9. Power-On Reset/Power-Down Reset Waveform
18
Figure 10. PVD Thresholds
19
4 Package
20
Package Selection
20
Table 3. Package Summary
20
Pinout Compatibility
22
I/O Speed
22
Table 4. I/O AC Characteristics
22
Alternate Function
24
Table 5. Alternate Function
24
Handling Unused Pins
25
Boot Mode Selection
25
Figure 11. Stm32Cubemx Example Screen-Shot
25
Table 6. Boot Modes
26
Boot Pin Connection
27
Embedded Boot Loader Mode
27
Table 7. Stm32F4Xxxx Bootloader Communication Peripherals
27
Figure 12. Boot Mode Selection Implementation Example
27
5 Debug Management
29
SWJ Debug Port (Serial Wire and JTAG)
29
Pinout and Debug Port Pins
29
SWJ Debug Port Pins
29
Figure 13. Host-To-Board Connection
29
Internal Pull-Up and Pull-Down Resistors on JTAG Pins
30
SWJ Debug Port Connection with Standard JTAG Connector
30
Table 8. Debug Port Pin Assignment
30
Figure 14. JTAG Connector Implementation
31
Clocks
32
HSE OSC Clock
32
Figure 15. HSE External Clock
32
Figure 16. HSE Crystal/Ceramic Resonators
32
LSE OSC Clock
33
Figure 17. LSE External Clock
33
Figure 18. LSE Crystal/Ceramic Resonators
33
Reference Design
34
Figure 19. Reference Schematic
34
Figure 20. Bill of Material
35
Recommended PCB Routing Guidelines for Stm32F4Xxxx Devices
36
PCB Stack-Up
36
Figure 21. Four Layer PCB Stack-Up Example
36
Crystal Oscillator
37
Power Supply Decoupling
37
Figure 22. Six Layer PCB Stack-Up Example
37
High Speed Signal Layout
38
SDMMC Bus Interface
38
Typical Layout for
38
DD /VSS Pair
38
Flexible Memory Controller (FMC) Interface
39
Quadrature Serial Parallel Interface (Quad SPI)
39
Embedded Trace Macrocell (ETM)
40
Package Layout Recommendation
41
BGA 216 0.8 MM Pitch Design Example
41
Table 9. BGA 216 0.8 MM Pitch Package Information
41
WLCSP143 0.4 MM Pitch Design Example
42
Table 10. Wafer Level Chip Scale Package Information
42
Figure 25. Via Fan-Out
42
Figure 26. FMC Signal Fan-Out Routing Example
42
Figure 27. 143-Bumps WLCSP, 0.40 MM Pitch Routing Example
44
Faq
45
Identify the Stm32F4Xxxx
45
Hardware Tools Available
45
Nucleao Boards
45
Discovery Kits
45
Evaluation Boards
45
Figure 28. STM32 ST-LINK Utility
45
Where to Find IBIS Models
46
MCU Does Not Work Properly
46
Table 11. MCU Does Not Work Properly
46
Conclusion
47
Revision History
48
Table 12. Document Revision History
48
Table 1. Applicable Products
49
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ST STM32F405 Series Specifications
General
Brand
ST
Model
STM32F405 Series
Category
Motherboard
Language
English
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