ST STM32H723ZG User Manual

Figure 10. Clock generation and clock tree
÷ DIVM1
÷ DIVM2
÷ DIVM3
PLLSRC
1 to 16
MHz
0
1
2
hsi_ck
csi_ck
hse_ck
ref1_ck
ref3_ck
ref2_ck
OSC32_IN
OSC32_OUT
OSC_IN
OSC_OUT
LSE
HSE
VSW (Backup)
HSI
CSI
HSI48
lse_ck
hse_ck
hsi_ck
csi_ck
hsi48_ck
CSS
hsi_ck
csi_ck
hse_ck
To
peripherals
To CPU,
busses and
peripherals
0
1
2
3
pll1_q_ck
pll1_r_ck
pll2_p_ck
pll2_q_ck
pll2_r_ck
pll3_p_ck
pll3_q_ck
pll3_r_ck
pll1_p_ck
1 to 16
MHz
1 to 16
MHz
SW
pll1_p_ck
sys_ck
0
1
2
3
4
5
÷ 1 to15
MCO2PRE
MCO2SEL
0
1
2
3
4
÷ 1 to15
MCO1PRE
MCO1SEL
pll[3:1]_q_ck
pll[3:2]_p_ck
pll[3:2]_r_ck
sys_ck
hse_ck
hsi_ker_ck
csi_ker_ck
per_ck
lsi_ck
lse_ck
hsi48_ck
MCO2
MCO1
I2S_CKIN
USB_PHY1
ETH_MII_TX_CLK
ulpi1_phy_ck
RCC
lse_ck
lsi_ck
hse_1M_ck
1
2
3
÷ 2 to 63
RTCPRE
RTCSRC
hsi_ker_ck
csi_ker_ck
hse_ck
CKPERSRC
per_ck
0
1
2
To
RTC/AWU
RTCEN
To
IWDG1
tempo
÷1,2,4,8
HSION
CSION
HSI48ON
HSIDIV
HSEON
SCGU (System Clock
Generation)
rcc_rtc_ck
PKEU (Peripheral Clock Enabling)
CSS
LSEON
pll1_r_ck
traceclkin
To TPIU
CRS
Clock
recovery
system
VCO
PLL1
DIVN1
FRACN1
VCO
PLL2
DIVN2
FRACN2
LSI
lsi_ck
tempo
LSION or IWDG1 activated
VDD Domain
SCEU (System Clock
Enabling)
D
D
The selected input can be changed on-the-fly without spurs on the output signal
sys_ck
pll2_p_ck
hse_ck
pll1_p_ck
csi_ck
lsi_ck
hsi_ck
lse_ck
hse_ck
pll1_q_ck
hsi48_ck
hsi_ck
csi_ck
hse_ck
0
1
2
3
x Represents the selected mux input after a system reset
0
0
VDD Domain
csi_ker_ck
tempo
tempo
hsi_ker_ck
tempo
HSIKERON
CSIKERON
D
ETH_MII_RX_CLK
ETH_RMII_REF_CLK
D
PKSU (Peripheral Kernel clock Selection)
DIVP1
DIVQ1
DIVR1
DIVP2
DIVQ2
DIVR2
VCO
PLL3
FRACN3
DIVP3
DIVQ3
DIVR3
DIVN3
Table 3. Clock connections
Pin
External component Comment
OSC32_IN
External clock input
LSE oscillator
LSE bypass input f≤ 1 MHz.
AN5419
Introduction
AN5419 - Rev 2
page 19/50

ST STM32H723ZG Specifications

General

Brand	ST
Model	STM32H723ZG
Category	Microcontrollers
Language	English