The STM32 Cortex-M4 instruction set PM0214
168/262 PM0214 Rev 10
3.10.18 VMOV Arm Core register to scalar
Transfers one word to a floating-point register from an Arm core register.
Syntax
VMOV{cond}{.32} Dd[x], Rt
Where:
• ‘cond’ is an optional condition code, see Conditional execution on page 65.
• 32 is an optional data size specifier.
• Dd[x] is the destination, where [x] defines which half of the doubleword is transferred,
as follows:
If x is 0, the lower half is extracted
If x is 1, the upper half is extracted.
• Rt is the source Arm core register.
Operation
This instruction transfers one word to the upper or lower half of a doubleword floating-point
register from an Arm core register.
Restrictions
Rt cannot be PC or SP.
Condition flags
These instructions do not change the flags.
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