The STM32 Cortex-M4 instruction set PM0214
60/262 PM0214 Rev 10
3.3 About the instruction descriptions
The following sections give more information about using the instructions:
• Operands on page 60
• Restrictions when using PC or SP on page 60
• Flexible second operand on page 60
• Shift operations on page 62
• Address alignment on page 65
• PC-relative expressions on page 65
• Conditional execution on page 65
• Instruction width selection on page 68
3.3.1 Operands
An instruction operand can be an Arm register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination
register. When there is a destination register in the instruction, it is usually specified before
the operands.
Operands in some instructions are flexible in that they can either be a register or a constant
(see Flexible second operand).
3.3.2 Restrictions when using PC or SP
Many instructions have restrictions on whether you can use the program counter (PC) or
stack pointer (SP) for the operands or destination register. See instruction descriptions for
more information.
Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must
be 1 for correct execution, because this bit indicates the required instruction set, and the
Cortex-M4 processor only supports thumb instructions.
3.3.3 Flexible second operand
Many general data processing instructions have a flexible second operand. This is shown
as operand2 in the description of the syntax of each instruction.
Operand2 can be a:
• Constant
• Register with optional shift
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