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ST STM32H757 User Manual
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PM0214 Rev 10
189/262
PM0214
The STM32 Cortex-M4 ins
truction set
261
3.1
1.9 SEV
Send Event.
Syntax
SEV{
cond
}
Where:
•
‘cond’
is an optional condition co
de, see
Conditional execution
on page 65
.
Operation
SEV is a hint instruction that
causes an event to be signaled
to all processors within a
multiprocessor system. It also sets
the local event register to 1, see
Power ma
nagement on
page 47
.
Condition flags
This instruction does not change the flags.
Examples
SEV ; Send Event
188
190
Table of Contents
Default Chapter
1
Table 1. Applicable Products
1
Table of Contents
2
About this Document
12
Typographical Conventions
12
List of Abbreviations for Registers
12
About the STM32 Cortex-M4 Processor and Core Peripherals
13
Figure 1. STM32 Cortex-M4 Implementation
13
Integrated Configurable Debug
14
System Level Interface
14
Cortex-M4 Processor Features and Benefits Summary
15
Cortex-M4 Core Peripherals
16
The Cortex-M4 Processor
17
Programmers Model
17
Processor Mode and Privilege Levels for Software Execution
17
Stacks
17
Core Registers
18
Table 2. Summary of Processor Mode, Execution Privilege Level, and Stack Usage
18
Table 3. Core Register Set Summary
18
Figure 2. Processor Core Registers
18
Table 4. PSR Register Combinations
20
Figure 3. APSR, IPSR and EPSR Bit Assignment
20
Figure 4. PSR Bit Assignment
20
Table 5. APSR Bit Definitions
21
Table 6. IPSR Bit Definitions
22
Table 7. EPSR Bit Definitions
23
Table 8. PRIMASK Register Bit Definitions
24
Table 9. FAULTMASK Register Bit Definitions
24
Figure 5. PRIMASK Bit Assignment
24
Figure 6. FAULTMASK Bit Assignment
24
Table 10. BASEPRI Register Bit Assignment
25
Table 11. CONTROL Register Bit Definitions
25
Figure 7. BASEPRI Bit Assignment
25
Exceptions and Interrupts
26
Data Types
26
The Cortex Microcontroller Software Interface Standard (CMSIS)
26
Memory Model
28
Figure 8. Memory Map
28
Memory Regions, Types and Attributes
29
Memory System Ordering of Memory Accesses
29
Table 12. Ordering of Memory Accesses
29
Behavior of Memory Accesses
30
Table 13. Memory Access Behavior
30
Software Ordering of Memory Accesses
31
Bit-Banding
32
Table 14. SRAM Memory Bit-Banding Regions
32
Table 15. Peripheral Memory Bit-Banding Regions
32
Figure 9. Bit-Band Mapping
33
Figure 10. Little-Endian Example
34
Memory Endianness
34
Synchronization Primitives
34
Programming Hints for the Synchronization Primitives
36
Table 16. CMSIS Functions for Exclusive Access Instructions
36
Exception Model
37
Exception States
37
Exception Types
37
Table 17. Properties of the Different Exception Types
38
Exception Handlers
39
Vector Table
40
Figure 11. Vector Table
40
Exception Priorities
41
Interrupt Priority Grouping
41
Exception Entry and Return
42
Figure 12. Cortex-M4 Stack Frame Layout
43
Fault Handling
44
Table 18. Exception Return Behavior
44
Fault Types
45
Table 19. Faults
45
Fault Escalation and Hard Faults
46
Fault Status Registers and Fault Address Registers
47
Lockup
47
Power Management
47
Table 20. Fault Status and Fault Address Registers
47
Entering Sleep Mode
48
Wakeup from Sleep Mode
48
External Event Input / Extended Interrupt and Event Input
49
Power Management Programming Hints
49
The STM32 Cortex-M4 Instruction Set
50
Instruction Set Summary
50
Table 21. Cortex-M4 Instructions
50
CMSIS Intrinsic Functions
58
Table 22. CMSIS Intrinsic Functions to Generate some Cortex-M4 Instructions
59
Table 23. CMSIS Intrinsic Functions to Access the Special Registers
59
About the Instruction Descriptions
60
Operands
60
Restrictions When Using PC or SP
60
Flexible Second Operand
60
Shift Operations
62
Figure 13. ASR #3
62
Figure 14. LSR #3
63
Figure 15. LSL #3
63
Figure 16. ROR #3
64
Figure 17. RRX #3
64
Address Alignment
65
PC-Relative Expressions
65
Conditional Execution
65
Table 24. Condition Code Suffixes
67
Instruction Width Selection
68
Memory Access Instructions
69
Table 25. Memory Access Instructions
69
Adr
70
LDR and STR, Immediate Offset
71
Table 26. Immediate, Pre-Indexed and Post-Indexed Offset Ranges
72
LDR and STR, Register Offset
73
LDR and STR, Unprivileged
74
LDR, PC-Relative
75
Table 27. Label-PC Offset Ranges
75
LDM and STM
76
PUSH and POP
78
LDREX and STREX
79
Clrex
80
General Data Processing Instructions
81
Table 28. Data Processing Instructions
81
ADD, ADC, SUB, SBC, and RSB
83
AND, ORR, EOR, BIC, and ORN
85
ASR, LSL, LSR, ROR, and RRX
86
Clz
87
CMP and CMN
88
MOV and MVN
89
Movt
91
REV, REV16, REVSH, and RBIT
92
SADD16 and SADD8
93
SHADD16 and SHADD8
94
SHASX and SHSAX
95
SHSUB16 and SHSUB8
96
SSUB16 and SSUB8
97
SASX and SSAX
98
TST and TEQ
99
UADD16 and UADD8
100
UASX and USAX
101
UHADD16 and UHADD8
102
UHASX and UHSAX
103
UHSUB16 and UHSUB8
104
Sel
105
Usad8
106
Usada8
107
USUB16 and USUB8
108
Multiply and Divide Instructions
109
Table 29. Multiply and Divide Instructions
109
MUL, MLA, and MLS
110
UMULL, UMAAL and UMLAL
111
SMLA and SMLAW
112
Smlad
114
SMLAL and SMLALD
115
SMLSD and SMLSLD
117
SMMLA and SMMLS
119
Smmul
120
SMUAD and SMUSD
121
SMUL and SMULW
122
UMULL, UMLAL, SMULL, and SMLAL
123
SDIV and UDIV
124
Saturating Instructions
125
Table 30. Saturating Instructions
125
SSAT and USAT
126
SSAT16 and USAT16
127
QADD and QSUB
128
QASX and QSAX
129
QDADD and QDSUB
130
UQASX and UQSAX
131
UQADD and UQSUB
132
Packing and Unpacking Instructions
134
Table 31. Packing and Unpacking Instructions
134
PKHBT and PKHTB
135
SXT and UXT
136
SXTA and UXTA
137
Bitfield Instructions
138
Table 32. Instructions that Operate on Adjacent Sets of Bits
138
BFC and BFI
139
SBFX and UBFX
140
SXT and UXT
141
B, BL, BX, and BLX
142
Branch and Control Instructions
142
Table 33. Branch and Control Instructions
142
Table 34. Branch Ranges
143
CBZ and CBNZ
144
TBB and TBH
147
Floating-Point Instructions
149
Table 35. Floating-Point Instructions
149
Vabs
151
Vadd
152
Vcmp, Vcmpe
153
VCVT, VCVTR between Floating-Point and Integer
154
VCVT between Floating-Point and Fixed-Point
155
Vcvtb, Vcvtt
156
VDIV
157
Vfma, Vfms
158
Vfnma, Vfnms
159
Vldm
160
Vldr
161
Vlma, Vlms
162
VMOV Immediate
163
VMOV Register
164
VMOV Scalar to Arm Core Register
165
VMOV Arm Core Register to Single Precision
166
VMOV Two Arm Core Registers to Two Single Precision
167
VMOV Arm Core Register to Scalar
168
Vmrs
169
Vmsr
170
Vmul
171
Vneg
172
Vnmla, Vnmls, Vnmul
173
Vpop
174
Vpush
175
Vsqrt
176
Vstm
177
Vstr
178
Vsub
179
Miscellaneous Instructions
180
Table 36. Miscellaneous Instructions
180
Bkpt
181
Cps
182
Dmb
183
Dsb
184
Isb
185
Mrs
186
Msr
187
Nop
188
Sev
189
Svc
190
Wfe
191
Wfi
192
Core Peripherals
193
About the STM32 Cortex-M4 Core Peripherals
193
Memory Protection Unit (MPU)
193
Table 37. STM32 Core Peripheral Register Regions
193
Table 38. Memory Attributes Summary
194
MPU Access Permission Attributes
195
Table 39. TEX, C, B, and S Encoding
195
Table 40. Cache Policy for Memory Attribute Encoding
195
MPU Mismatch
196
Table 41. AP Encoding
196
Updating an MPU Region
196
Figure 18. Subregion Example
198
MPU Design Hints and Tips
199
Table 42. Memory Region Attributes for STM32
199
MPU Type Register (MPU_TYPER)
200
MPU Control Register (MPU_CTRL)
201
MPU Region Number Register (MPU_RNR)
202
MPU Region Base Address Register (MPU_RBAR)
203
MPU Region Attribute and Size Register (MPU_RASR)
204
Table 43. Example SIZE Field Values
205
MPU Register Map
206
Table 44. MPU Register Map and Reset Values
206
Nested Vectored Interrupt Controller (NVIC)
208
Table 45. NVIC Register Summary
208
Accessing the Cortex-M4 NVIC Registers Using CMSIS
209
Table 46. CMSIS Access NVIC Functions
209
Interrupt Set-Enable Register X (Nvic_Iserx)
210
Interrupt Clear-Enable Register X (Nvic_Icerx)
211
Interrupt Set-Pending Register X (Nvic_Isprx)
212
Interrupt Clear-Pending Register X (Nvic_Icprx)
213
Interrupt Active Bit Register X (Nvic_Iabrx)
214
Figure 19. Mapping of IP[N] Fields in Nvic_Iprx Registers
215
Interrupt Priority Register X (Nvic_Iprx)
215
Table 47. Nvic_Iprx Bit Assignment
215
Software Trigger Interrupt Register (NVIC_STIR)
216
Level-Sensitive and Pulse Interrupts
217
NVIC Design Hints and Tips
218
Table 48. CMSIS Functions for NVIC Control
218
NVIC Register Map
219
Table 49. NVIC Register Map and Reset Values
219
System Control Block (SCB)
221
Table 50. Summary of the System Control Block Registers
221
Auxiliary Control Register (ACTLR)
222
CPUID Base Register (CPUID)
224
Interrupt Control and State Register (ICSR)
225
Vector Table Offset Register (VTOR)
227
Application Interrupt and Reset Control Register (AIRCR)
228
Table 51. Priority Grouping
229
System Control Register (SCR)
230
Configuration and Control Register (CCR)
231
System Handler Priority Registers (Shprx)
233
Table 52. System Fault Handler Priority Fields
233
System Handler Control and State Register (SHCSR)
235
Configurable Fault Status Register (CFSR; UFSR+BFSR+MMFSR)
237
Figure 20. CFSR Subregisters
237
Usage Fault Status Register (UFSR)
238
Bus Fault Status Register (BFSR)
239
Memory Management Fault Address Register (MMFSR)
240
Hard Fault Status Register (HFSR)
241
Bus Fault Address Register (BFAR)
242
Memory Management Fault Address Register (MMFAR)
242
Auxiliary Fault Status Register (AFSR)
243
System Control Block Design Hints and Tips
243
SCB Register Map
244
Table 53. SCB Register Map and Reset Values
244
Systick Timer (STK)
246
Table 54. System Timer Registers Summary
246
Systick Control and Status Register (STK_CTRL)
247
Systick Reload Value Register (STK_LOAD)
248
Systick Current Value Register (STK_VAL)
249
Systick Calibration Value Register (STK_CALIB)
250
Systick Design Hints and Tips
250
Systick Register Map
251
Table 55. Systick Register Map and Reset Values
251
Floating Point Unit (FPU)
252
Table 56. Cortex-M4F Floating-Point System Registers
252
Coprocessor Access Control Register (CPACR)
253
Floating-Point Context Control Register (FPCCR)
253
Floating-Point Context Address Register (FPCAR)
255
Floating-Point Status Control Register (FPSCR)
255
Table 57. Effect of a Floating-Point Comparison on the Condition Flags
256
Enabling the FPU
257
Floating-Point Default Status Control Register (FPDSCR)
257
Enabling and Clearing FPU Exception Interrupts
258
Revision History
260
Table 58. Document Revision History
260
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ST STM32H757 Specifications
General
Brand
ST
Model
STM32H757
Category
Computer Hardware
Language
English
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