ST STM32H757 User Manual

PM0214 Rev 10 219/262
PM0214 Core peripherals
261
4.3.11 NVIC register map
This table shows the NVIC register map and reset values. The base address of the main
NVIC register block is 0xE000E100. The NVIC_STIR register is located in a separate block
at 0xE000EF00.
Table 49. NVIC register map and reset values
Offset Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
11
10
9 8 7 6 5 4 3 2 1 0
0x100
NVIC_ISER0 SETENA[31:0]
Reset Value 00000000000000000000000000000000
0x104
NVIC_ISER1 SETENA[63:32]
Reset Value 00000000000000000000000000000000
:: :
0x11C
NVIC_ISER7 Reserved SETENA [239:224]
Reset Value -------- 00000000000000000
0x180
NVIC_ICER0 CLRENA[31:0]
Reset Value 00000000000000000000000000000000
0x184
NVIC_ICER1 CLRENA[63:32]
Reset Value 00000000000000000000000000000000
:: :
0x19C
NVIC_ICER7 Reserved CLRENA [239:224]
Reset Value -------- 00000000000000000
0x200
NVIC_ISPR0 SETPEND[31:0]
Reset Value 00000000000000000000000000000000
0x204
NVIC_ISPR1 SETPEND[63:32]
Reset Value 00000000000000000000000000000000
:: :
0x21C
NVIC_ISPR7 Reserved SETPEND [239:224]
Reset Value -------- 00000000000000000
0x280
NVIC_ICPR0 CLRPEND[31:0]
Reset Value 00000000000000000000000000000000
0x284
NVIC_ICPR1 CLRPEND[63:32]
Reset Value 00000000000000000000000000000000
:: :
0x29C
NVIC_ICPR7 Reserved CLRPEND [239:224]
Reset Value -------- 00000000000000000
0x300
NVIC_IABR0 ACTIVE[31:0]
Reset Value 00000000000000000000000000000000

ST STM32H757 Specifications

General

Brand	ST
Model	STM32H757
Category	Computer Hardware
Language	English