Supermicro SuperServer SYS-121H-TNR - Page 47

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Chapter 3: Maintenance and Component Installation
DDR5 Memory Population Table (with Max Series ((HBM)) CPUs and 32 DIMMs Installed)
1 CPU: Memory Population Sequence
1 CPU & 1 DIMM
P1-DIMMA1
P1-DIMME1
1 CPU & 2 DIMMs
P1-DIMMA1/P1-DIMMG1
P1-DIMMC1/P1-DIMME1
1 CPU & 4 DIMMs P1-DIMMA1/P1-DIMMC1/P1-DIMME1/P1-DIMMG1
1 CPU & 8 DIMMs P1-DIMMA1/P1-DIMMB1/P1-DIMMC1/P1-DIMMD1/P1-DIMME1/P1-DIMMF1/P1-DIMMG1/P1-DIMMH1
1 CPU & 16 DIMMs
P1-DIMMA1/P1-DIMMA2/P1-DIMMB1/P1-DIMMB2/P1-DIMMC1/P1-DIMMC2/P1-DIMMD1/P1-DIMMD2/P1-DIMME1/P1-
DIMME2/P1-DIMMF1/P1-DIMMF2/P1-DIMMG1/P1-DIMMG2/P1-DIMMH1/P1-DIMMH2
2 CPUs:
(Recommended)
Memory Population Sequence
2 CPUs & 2 DIMMs
CPU1: P1-DIMMA1, CPU2: P2-DIMMA1
CPU1: P1-DIMME1, CPU2: P2-DIMME1
2 CPUs & 4 DIMMs
CPU1: P1-DIMMA1/P1-DIMMG1, CPU2: P2-DIMMA1/P2-DIMMG1
CPU1: P1-DIMMC1/P1-DIMME1, CPU2: P2-DIMMC1/P2-DIMME1
2 CPUs & 8 DIMMs
CPU1: P1-DIMMA1/P1-DIMMC1/P1-DIMME1/P1-DIMMG1
CPU2: P2-DIMMA1/P2-DIMMC1/P2-DIMME1/P2-DIMMG1
2 CPUs & 16 DIMMs
CPU1: P1-DIMMA1/P1-DIMMB1/P1-DIMMC1/P1-DIMMD1/P1-DIMME1/P1-DIMMF1/P1-DIMMG1/P1-DIMMH1
CPU2: P2-DIMMA1/P2-DIMMB1/P2-DIMMC1/P2-DIMMD1/P2-DIMME1/P2-DIMMF1/P2-DIMMG1/P2-DIMMH1
2 CPUs & 32 DIMMs
CPU1: P1-DIMMA1/P1-DIMMA2/P1-DIMMB1/P1-DIMMB2/P1-DIMMC1/P1-DIMMC2/P1-DIMMD1/P1-DIMMD2/P1-
DIMME1/P1-DIMME2/P1-DIMMF1/P1-DIMMF2/P1-DIMMG1/P1-DIMMG2/P1-DIMMH1/P1-DIMMH2
CPU2: P2-DIMMA1/P2-DIMMA2/P2-DIMMB1/P2-DIMMB2/P2-DIMMC1/P2-DIMMC2/P2-DIMMD1/P2-DIMMD2/P2-
DIMME1/P2-DIMME2/P2-DIMMF1/P2-DIMMF2/P2-DIMMG1/P2-DIMMG2/P2-DIMMH1/P2-DIMMH2
Notes:
1. Max Series (HBM) CPU supports 1DPC (4800MT/s) / 2DPC (4400MT/s) to optimize the
memory bandwidth. Max Series (HBM) CPU supports 1, 2, 4, 8, or 16 DIMMs in Flat
Mode as well as Cache Mode, and 0 DIMMs in HBM-Only mode. HBM-Only mode runs
exclusively using HBM memory. Crow Pass / DDR-T is not supported on SPR+HBM.
2. SPR+HBM supports 4, 8, or 16 DIMMs in all modes (Flat / Cached and Quadrant /
SNC4)
"4 DIMMs -> populate 1 DIMM/iMC
8 DIMMs -> populate 1 DIMM/Channel, 2 DIMM/iMC
16 DIMMs -> populate 1 DIMM/Channel, 4 DIMM/iMC"
3. All other congurations not listed above are not supported.
4. For 2S design, each socket has to be populated identically.