Synopsys TSMC180 - Loadcal Operation

DWC ADC 12b5M SAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 20-30
Figure 11 - Full calibration cycle timing diagram
The calibration value can be loaded externally when loadcal signal is high.
After setting loadcal to high, the offset calibration word is loaded into the internal registers
(bvosi6…0). In the next clock falling edge, bvos6…0 is updated with the external calibration
word.
The loadcal should be asserted for at least one clock cycle. Below is the timing diagram for
the loadcal operation. The minimum setup (tsetup) time is 1.5ns and hold (thold) time is 2ns
for loadcal signal. Taking this into account, loadcal can only be changed when clock is low.
The loadcal functionality is useful during Deep Power Down Mode but also if the user needs
to store different calibration values (e.g., for single-ended and differential input mode). By
ensuring the timing constrains between loadcal and soc (in the figure below bvos<6:0> are
updated in the first clock falling edge after soc detection) it is possible to perform the loadcal
operation for successive conversions cycles. This can be useful if the application demands
successive conversion cycles and at the same time changing between single-ended and
differential input mode.
Figure 12 – Loadcal operation.
1 2
. . .
8
. . .
. . .
9
1
st
offset
measurement cycle
10
. . .
2
nd
offset
measurement cycle
. . .
. . .
80 81
9
th
offset
measurement cycle
(bvos6...bvos0)
avg
. . .. . .
. . . . . .
1000000
Calibration Cycle
. . .. . .
Output Data n
clk
resetcal
startcal
c
a
l
o
n
bvos6...bvos0
b11...b0
3
. . . . . .
eoc
17 18 19
. . .
. . .
. . .
. . .
. . .
. . .
. . .
72 73 74
. . .
. . .
. . .
. . .
. . .
. . .
. . .
calon
. . .
soc
loadcalcal pulse length
1 clk cycle minimum
clk
External calibration value
loadcal
bvosi<6:0>
bvos<6:0>
Sampled external calibration value with the clock falling edge
tholdtsetup
eoc
soc