Theory of Operation—2465B/2467B Service 
the various devices and circuit functions. The controlling 
signals are generated as a result of the Microprocessor 
placing specific addresses on the Address Bus. Figure 3-2 
illustrates the enables and strobes generated by the 
Address Decode circuitry. 
bit A15 HI) select one of two read-only memories (ROM), 
U2160,
 or U2260. When the VMA (Valid Memory Address) 
and E (Enable) outputs from the Microprocessor go HI, the 
selected ROM is enabled, and the data from the selected 
address location is read from the ROM. 
Address decoding is performed by a programable array 
logic device, a three-line-to-eight-line decoder, and a
 four-
line-to-sixteen-line decoder attached to the Address Bus. 
The five most significant address bits are decoded by 
U2250.
 This device initially separates the total 
addressable-memory space (64K-bytes) into thirty-two, 
2K-byte blocks. Addresses in the top 32K-bytes (address 
The programmable array logic device also generates 
the OE and WE signals to the random-access memory 
(RAM). This RAM can be accessed with addresses 8000 
to 9FFF if either PBO, PB1, or PB2 signals are HI. In this 
mode ROMS, U2160 and U2260 are not accessible in this 
address range. 
HEX 
ADDRESS 
DECODED BY 
U2250 
HEX 
ADDRESS 
0000 
07FF 
0800 
0FFF 
1000 
7FFF 
8000 
FFFF 
RAM-U2460 
ADDRESS 
DECODING 
(U2550) 
RESERVED 
FOR OPTIONS 
R0MS-U2160 
AND U2260 
RAM-U2460 
0800 
083F 
0840 
0B7F 
0880 
08BF 
08C0 
08FF 
0900 
093F 
0940 
097F 
0980 
09C0 
09FF 
0A00 
0BFF 
0C00 
y ODFF 
\ 0E00 
0FFF 
DECODED BY 
U2550 
HEX 
ADDRESS 
DMUX2 OFF 
DAC MSB CLK (087F) 
DAC LSB CLK (0880) 
PORT 1 CLK (08C0) 
ROS 1 CLK (0900) 
ROS 2 CLK (0940) 
PORT 2 CLK (0980) 
FURTHER ADDRESS 
DECODING (U2660) 
OVERLAY OF 
0800-09FF 
OVERLAY OF 
0800-09FF 
OVERLAY OF 
0800-09FF 
/ -
/ 09C0 
/
 09C1 
/ 
09C2 
09C3 
09C4 
09C5 
09C6 
09C7 
09C8 
09C9 
09CA 
09CB 
09CC 
09CD 
09CE 
09CF 
\ 09D0 
09DF 
V
 09E0 
\ 09EF 
\ 09F0 
V
09FF 
DECODED BY 
U2660 
DMUX2 ON 
DMUXO OFF 
DMUXO ON 
PORT 3 IN 
DMUX1 OFF 
DMUX1 ON 
LED CLK 
DISP SEQ CLK 
ATN CLK 
CH 2 PA CLK 
CH 1 PA CLK 
B SWP CLK 
A SWP CLK 
B TRIG CLK 
A TRIG CLK 
TRIG STAT STRB 
OVERLAY OF 09C0-09CF 
OVERLAY OF 09C0-09CF 
OVERLAY OF 09C0-09CF 
6019-09 
Figure 3-2. Address decoding. 
3-7