Theory of Operation—2465B/2467B Service
Of the bottom 32K-byt.es of addresses, only the lowest
4K-bytes are further decoded. Addresses in the lowest
2K-byte block of addresses will cause U2250 to generate
an enable signal to the RAM, U2460. Addresses in the
next 2K-byte block of addresses will enable U2550 to do
the next stage of address decoding.
The level of decoding performed by U2550 uses
address bits A6, A7, and A8 to separate the addresses
within the 2K-byte block of addresses 0800 thru OFFF into
32 groups of 64 addresses. Address bits A9 and A10 are
not used in the decoding scheme, so each of these 32
blocks is not uniquely identified. This results in four dupli-
cate sections within the address block, each consisting of
eight groups of 64 addresses. The upper three sections in
the address space are never used; therefore, decoding by
U2550 may be more simply thought of as eight groups of
64 address locations. Addresses within these eight
groups generate control signals to other portions of the
instrument.
The final level of address decoding is done by four-line-
to-sixteen-line decoder U2660. When enabled by the Y7
output of U2550, this decoder separates the highest 64-
address group decoded by U2550 into 16 individual control
signals. In this level of decoding, address bits A4 and A5
are not decoded, so that the 64 possible addresses
consist of four overlayed blocks of 16 addresses each.
Each of the control signals generated by the Address
Decode circuitry are present only as long as the specific
address defining that signal is present on the Address
Bus.
However, one of the addressable control signals
decoded by U2550 and five of the addressable control
sig-
nals decoded by U2660 are used to either set or reset
flip-flops U2650A, U2650B, and U2650D. The control
sig-
nals are, in effect, latched and remain present to enable
multiplexers
U2521,
U2530, (diagram 2) and U170
(diagram 4). When enabled, these multiplexers route ana-
log control signals from DAC (digital-to-analog converter)
U2101 (diagram 2) to the various analog control circuits.
Read-only Memory (ROM)
The Read-only Memory consists of one, 128K-byte
ROM or two, 64K-byte ROMs that contain operating
instructions (firmware) used to control processor (and thus
oscilloscope) operation. Addresses from the Microproces-
sor that fall within the top 32K-bytes of addressable space
cause one of the two read-only memory integrated circuits
to be enabled. (See Address Decode description.) Instruc-
tions are read out of the enabled ROM (or PROM) IC from
the address location present on its 16 address input pin
(A0 through A14, Page Select). The eight-bit data byte
from the addressed locations is placed onto the Buffered
Data bus (BDO through BD7) to be read by the Micropro-
cessor.
Random-Access Memory (RAM)
The RAM consists of integrated circuit U2460 and pro-
vides the Microprocessor with 8K-bytes of battery backed
up temporary storage space for data that is developed
during the execution of a routine. The RAM is enabled
whenever an address in the lowest 2K-byte of addresses
is placed on the Address Bus or whenever an address of
8000 thru 9FFF is placed on the Address bus with either
PB0,
PB1, or PB2 set HI. When writing into the RAM, the
write-enable signal (WE) on pin 27 of U2460 is set LO
along with the chip enable (CE1) signal on pin 20. At the
same time, the output-enable (OE) on pin 22 is HI to dis-
able the RAM output drivers. Data is then written to the
location addressed by the Microprocessor. If data is to be
read from the RAM, the WE signal is set HI to place the
RAM in the read mode, and the OE signal is set LO to
enable the output drivers. This places the data from the
addressed location on the buffered Data Bus where it can
be read by the Microprocessor.
The RAM also provides non-volatile storage for the
calibration constants and the power-down front-panel set-
tings.
When power is applied to the instrument, the
Microprocessor reads the calibration constants and
gen-
erates control voltages to set up the analog circuitry. The
front-panel settings that were present at power-off are
recalled and the instrument is set to the operating mode
previous power off.
Battery Circuitry
The Battery circuit composed of BT2570, R2770,
CR2770, CR2370,
CR2371,
and C2470 provides the
standby voltage necessary to maintain the contents of the
CMOS RAM (U2460). The circuit composed of R2530,
U2620C, R2504, and R2506 provides the microprocessor
a means of monitoring the battery voltage to detect when
the battery needs to be replaced.
Timing Logic
The Timing Logic circuit composed of U2440B, and
U2540F generates time- and mode-dependent signals from
control signals output from the Microprocessor. The
enable (E) signal output from the Microprocessor is a 1.25
MHz square wave used to synchronize oscilloscope func-
tions to processor timing.
3-8
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