LMK04821
,
LMK04826
,
LMK04828
www.ti.com
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
9.7.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
This register has CLKin_SEL1 controls and register readback SDIO pin type.
Table 40. Register 0x149
POR
BIT NAME DESCRIPTION
DEFAULT
7 NA 0 Reserved
Sets the SDIO pin to open drain when during SPI readback in 3 wire mode.
6 SDIO_RDBK_TYPE 1 0: Output, push-pull
1: Output, open drain.
This set the output value of the CLKin_SEL1 pin. This register only applies if
CLKin_SEL1_TYPE is set to an output mode.
Field Value Output Format
0 (0x00) Logic Low
1 (0x01) CLKin1 LOS
2 (0x02) CLKin1 Selected
5:3 CLKin_SEL1_MUX 0
3 (0x03) DAC Locked
4 (0x04) DAC Low
5 (0x05) DAC High
6 (0x06) SPI Readback
7 (0x07) Reserved
This sets the IO type of the CLKin_SEL1 pin.
Field Value Configuration Function
0 (0x00) Input
Input mode, see Input Clock
1 (0x01) Input /w pull-up resistor Switching - Pin Select Mode for
description of input mode.
2:0 CLKin_SEL1_TYPE 2 2 (0x02) Input /w pull-down resistor
3 (0x03) Output (push-pull)
Output modes; see the
4 (0x04) Output inverted (push-pull)
CLKin_SEL1_MUX register for
5 (0x05) Reserved
description of outputs.
6 (0x06) Output (open drain)
Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 71
Product Folder Links: LMK04821 LMK04826 LMK04828
To Next Page
Loading...
Need help?
General
