LMK04821
,
LMK04826
,
LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
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9.7.5 RESET_MUX, RESET_TYPE
This register contains control of the RESET pin.
Table 41. Register 0x14A
POR
BIT NAME DEFAUL DESCRIPTION
T
7:6 NA 0 Reserved
This sets the output value of the RESET pin. This register only applies if RESET_TYPE is set to an
output mode.
Field Value Output Format
0 (0x00) Logic Low
1 (0x01) Reserved
5:3 RESET_MUX 0
2 (0x02) CLKin2 Selected
3 (0x03) DAC Locked
4 (0x04) DAC Low
5 (0x05) DAC High
6 (0x06) SPI Readback
This sets the IO type of the RESET pin.
Field Value Configuration Function
0 (0x00) Input
Reset Mode
1 (0x01) Input /w pull-up resistor
Reset pin high = Reset
2:0 RESET_TYPE 2 2 (0x02) Input /w pull-down resistor
3 (0x03) Output (push-pull)
Output modes; see the
4 (0x04) Output inverted (push-pull)
RESET_MUX register for
5 (0x05) Reserved
description of outputs.
6 (0x06) Output (open drain)
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