Region Pointer (RPTR)
Low Header
4 kB
App Code Offset (AOFF)
Region Pointer (RPTR)
High Header
4 kB
App Code Offset (AOFF)
0x000000
0x000004
0x000000
0x000FFC
0x001000
0x001004
0x001FFC
0x002000
RPTR+AOFF
RPTR+AOFF+CSIZE
Application Code
(max. 64 kB)
ID, Header, &
Configuration Data
(max. 4 kB)
Figure 9-57. Flash Memory Organization
There are two 4 kB header blocks starting at address 0x000000h. The Low Header 4 kB block is at address
0x000000h and the High Header 4 kB block is at 0x001000h. Each header contains a Region Pointer (RPTR)
that holds the address of the physical location in memory where the low region application code resides. Each
also contains an Application Code Offset (AOFF) that contains the physical offset inside the region where the
TPS65982 application code resides. The TPS65982 firmware physical location in memory is RPTR + AOFF. The
first sections of the TPS65982 application code contain device configuration settings where CSIZE is maximum
of 4 kB. This configuration determines the devices default behavior after power-up and can be customized using
the TPS65982 Configuration Tool. These pointers may be valid or invalid. The Flash Read flow handles reading
and determining whether a region is valid and contains good application code.
9.4.6 Flash Memory Read
The TPS65982 first attempts to load application code from the low region of the attached flash memory. If any
part of the read process yields invalid data, the TPS65982 will abort the low region read and attempt to read
from the high region. If both regions contain invalid data the device carries out the Invalid Memory flow. Figure
9-58 shows the flash memory read flow.
www.ti.com
TPS65982
SLVSD02E – MARCH 2015 – REVISED AUGUST 2021
Copyright © 2021 Texas Instruments Incorporated
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