Texas Instruments TMS320C6745 DSP

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TMS320C6745/C6747 DSP

Technical Reference Manual

Literature Number: SPRUH91D

March 2013–Revised September 2016

Main Page

Default Chapter2
- Table of Contents2
- Purpose of the Peripheral16
- 29.1.3 Functional Block Diagram17
- 29.2.2 Signal Descriptions17
- 29.2.9 DMA Event Support17
Preface64
- Introduction66
2 DSP Subsystem68
- Tms320C674X Megamodule Block Diagram69
- Introduction69
- DSP Interrupt Map70
- TMS320C6745/C6747 DSP System Interconnect Matrix77
- Introduction77
- System Interconnect Block Diagram78
4 System Memory79
- Introduction80
- Peripherals81
5 Memory Protection Unit (MPU)82
- MPU Block Diagram83
- Introduction83
- MPU Memory Regions84
- MPU Default Configuration84
- Device Master Settings85
  - Memory Protection Ranges85
- Permission Fields86
- Request Type Access Controls86
  - Permission Structures86
  - Protection Check87
- MPU_BOOTCFG_ERR Interrupt Sources88
  - Invalid Accesses and Exceptions88
- Memory Protection Unit 1 (MPU1) Registers89
- Memory Protection Unit 2 (MPU2) Registers89
  - MPU Registers89
- Revision ID Register (REVID)91
- Configuration Register (CONFIG)91
- Revision ID Register (REVID) Field Descriptions91
- Configuration Register (CONFIG) Field Descriptions91
- Interrupt Raw Status/Set Register (IRAWSTAT)92
- Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions92
- Interrupt Enable Status/Clear Register (IENSTAT)93
- Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions93
- Interrupt Enable Set Register (IENSET)94
- Interrupt Enable Clear Register (IENCLR)94
- Interrupt Enable Set Register (IENSET) Field Descriptions94
- Interrupt Enable Clear Register (IENCLR) Field Descriptions94
  - Fixed Range End Address Register (FXD_MPEAR)95
- Fixed Range Start Address Register (FXD_MPSAR)95
  - Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)96
- Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions96
  - Programmable Range N Start Address Registers (Progn_Mpsar)97
- MPU1 Programmable Range N Start Address Register (Progn_Mpsar)97
- MPU2 Programmable Range N Start Address Register (Progn_Mpsar)97
- MPU1 Programmable Range N Start Address Register (Progn_Mpsar) Field Descriptions97
- MPU2 Programmable Range N Start Address Register (Progn_Mpsar) Field Descriptions97
  - Programmable Range N End Address Registers (Progn_Mpear)98
- MPU1 Programmable Range N End Address Register (Progn_Mpear)98
- MPU2 Programmable Range N End Address Register (Progn_Mpear)98
- MPU1 Programmable Range N End Address Register (Progn_Mpear) Field Descriptions98
- MPU2 Programmable Range N End Address Register (Progn_Mpear) Field Descriptions98
  - Programmable Range N Memory Protection Page Attributes Register (Progn_Mppa)99
- Programmable Range Memory Protection Page Attributes Register (Progn_Mppa)99
- Programmable Range Memory Protection Page Attributes Register (Progn_Mppa) Field Descriptions99
  - Fault Address Register (FLTADDRR)100
- Fault Address Register (FLTADDRR) Field Descriptions100
  - Fault Status Register (FLTSTAT)101
- Fault Status Register (FLTSTAT) Field Descriptions101
  - Fault Clear Register (FLTCLR)102
- Fault Clear Register (FLTCLR) Field Descriptions102
6 Device Clocking103
- Overview104
- Device Clock Inputs104
- System Clock Domains104
  - Frequency Flexibility105
- Overall Clocking Diagram105
- Example PLL Frequencies106
  - Peripheral Clocking107
    - 6.3.1 USB Clocking107
- USB Clocking Diagram107
- USB Clock Multiplexing Options108
  - 6.3.2 EMIFB Clocking109
- EMIFB Clocking Diagram110
- EMIFB MCLK Frequencies110
  - 6.3.3 EMIFA Clocking111
- EMIFA Clocking Diagram111
- EMIFA Frequencies111
  - 6.3.4 EMAC Clocking112
- EMAC Clocking Diagram112
- EMAC Reference Clock Frequencies113
  - 6.3.5 I/O Domains114
- Peripherals114
7 Phase-Locked Loop Controller (PLLC)115
- Introduction116
- PLL0 Control116
- PLL0 Structure117
  - 7.2.1 Device Clock Generation118
- System PLLC0 Output Clocks118
  - 7.2.2 Steps for Changing PLL0 Domain Frequency119
  - Locking/Unlocking PLL Register Access120
  - PLLC Registers121
- PLL Controller (PLLC) Registers121
  - Revision Identification Register (REVID)122
  - Reset Type Status Register (RSTYPE)122
- Revision Identification Register (REVID) Field Descriptions122
- Reset Type Status Register (RSTYPE) Field Descriptions122
  - PLL Control Register (PLLCTL)123
- PLL Control Register (PLLCTL) Field Descriptions123
  - OBSCLK Select Register (OCSEL)124
- OBSCLK Select Register (OCSEL) Field Descriptions124
  - PLL Multiplier Control Register (PLLM)125
  - PLL Pre-Divider Control Register (PREDIV)125
- PLL Multiplier Control Register (PLLM) Field Descriptions125
- PLL Pre-Divider Control Register (PREDIV) Field Descriptions125
  - PLL Controller Divider 1 Register (PLLDIV1)126
  - PLL Controller Divider 2 Register (PLLDIV2)126
- PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions126
- PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions126
  - PLL Controller Divider 3 Register (PLLDIV3)127
  - PLL Controller Divider 4 Register (PLLDIV4)127
- PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions127
- PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions127
  - PLL Controller Divider 5 Register (PLLDIV5)128
  - PLL Controller Divider 6 Register (PLLDIV6)128
  - PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions128
  - PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions128
  - PLL Controller Divider 7 Register (PLLDIV7)129
  - PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions129
  - Oscillator Divider 1 Register (OSCDIV)130
- Oscillator Divider 1 Register (OSCDIV) Field Descriptions130
  - PLL Post-Divider Control Register (POSTDIV)131
  - PLL Controller Command Register (PLLCMD)131
- PLL Post-Divider Control Register (POSTDIV) Field Descriptions131
- PLL Controller Command Register (PLLCMD) Field Descriptions131
  - PLL Controller Status Register (PLLSTAT)132
- PLL Controller Status Register (PLLSTAT) Field Descriptions132
  - PLL Controller Clock Align Control Register (ALNCTL)133
- PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions133
  - PLLDIV Ratio Change Status Register (DCHANGE)134
- PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions134
  - Clock Enable Control Register (CKEN)135
- Clock Enable Control Register (CKEN) Field Descriptions135
  - Clock Status Register (CKSTAT)136
- Clock Status Register (CKSTAT) Field Descriptions136
  - SYSCLK Status Register (SYSTAT)137
- SYSCLK Status Register (SYSTAT) Field Descriptions137
  - Emulation Performance Counter 0 Register (EMUCNT0)138
  - Emulation Performance Counter 1 Register (EMUCNT1)138
- Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions138
- Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions138
8 Power and Sleep Controller (PSC)139
- Introduction140
- Power Domain and Module Topology140
- PSC0 Default Module Configuration140
- PSC1 Default Module Configuration141
  - 8.2.1 Power Domain States142
  - 8.2.2 Module States142
  - SPRUH91D - March 2013 - Revised September 2016142
- Module States143
  - Executing State Transitions144
    - 8.3.1 Power Domain State Transitions144
    - 8.3.2 Module State Transitions144
  - Icepick Emulation Support in the PSC145
  - PSC Interrupts145
    - 8.5.1 Interrupt Events145
- Icepick Emulation Commands145
- PSC Interrupt Events145
  - 8.5.2 Interrupt Registers146
  - 8.5.3 Interrupt Handling147
  - PSC Registers148
- Power and Sleep Controller 0 (PSC0) Registers148
- Power and Sleep Controller 1 (PSC1) Registers148
  - Revision Identification Register (REVID)149
  - Interrupt Evaluation Register (INTEVAL)149
- Revision Identification Register (REVID) Field Descriptions149
- Interrupt Evaluation Register (INTEVAL) Field Descriptions149
  - PSC0 Module Error Pending Register 0 (Modules 0-15) (MERRPR0)150
  - PSC1 Module Error Pending Register 0 (Modules 0-31) (MERRPR0)150
- PSC0 Module Error Pending Register 0 (MERRPR0)150
- PSC1 Module Error Pending Register 0 (MERRPR0)150
- PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions150
  - PSC0 Module Error Clear Register 0 (Modules 0-15) (MERRCR0)151
  - PSC1 Module Error Clear Register 0 (Modules 0-31) (MERRCR0)151
- PSC0 Module Error Clear Register 0 (MERRCR0)151
- PSC1 Module Error Clear Register 0 (MERRCR0)151
- PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions151
  - Power Error Pending Register (PERRPR)152
  - Power Error Clear Register (PERRCR)152
- Power Error Pending Register (PERRPR) Field Descriptions152
- Power Error Clear Register (PERRCR) Field Descriptions152
  - Power Domain Transition Command Register (PTCMD)153
- Power Domain Transition Command Register (PTCMD) Field Descriptions153
  - Power Domain Transition Status Register (PTSTAT)154
- Power Domain Transition Status Register (PTSTAT) Field Descriptions154
  - Power Domain 0 Status Register (PDSTAT0)155
- Power Domain 0 Status Register (PDSTAT0) Field Descriptions155
  - Power Domain 1 Status Register (PDSTAT1)156
- Power Domain 1 Status Register (PDSTAT1) Field Descriptions156
  - Power Domain 0 Control Register (PDCTL0)157
- Power Domain 0 Control Register (PDCTL0) Field Descriptions157
  - Power Domain 1 Control Register (PDCTL1)158
- Power Domain 1 Control Register (PDCTL1) Field Descriptions158
  - Power Domain 0 Configuration Register (PDCFG0)159
- Power Domain 0 Configuration Register (PDCFG0) Field Descriptions159
  - Power Domain 1 Configuration Register (PDCFG1)160
- Power Domain 1 Configuration Register (PDCFG1) Field Descriptions160
  - Module Status N Register (Mdstatn)161
- Module Status N Register (Mdstatn) Field Descriptions161
  - PSC0 Module Control N Register (Modules 0-15) (Mdctln)162
- PSC0 Module Control N Register (Mdctln)162
- PSC0 Module Control N Register (Mdctln) Field Descriptions162
  - PSC1 Module Control N Register (Modules 0-31) (Mdctln)163
- PSC1 Module Control N Register (Mdctln)163
- PSC1 Module Control N Register (Mdctln) Field Descriptions163
9 Power Management164
- Introduction165
- Power Consumption Overview165
- PSC and PLLC Overview165
- Features166
- Power Management Features166
10 System Configuration (SYSCFG) Module170
- 10.1 Introduction171
- 10.2 Protection172
- System Configuration (SYSCFG) Module Register Access172
  - 10.2.1 Requirements to Access SYSCFG Registers173
  - 10.3 Master Priority Control174
- Master Ids174
  - 10.4 Interrupt Support175
- Default Master Priority175
  - 10.5 SYSCFG Registers176
- System Configuration Module (SYSCFG) Registers176
  - Revision Identification Register (REVID)177
  - Device Identification Register 0 (DEVIDR0)177
- Revision Identification Register (REVID) Field Descriptions177
- Device Identification Register 0 (DEVIDR0) Field Descriptions177
  - Boot Configuration Register (BOOTCFG)178
  - Silicon Revision Identification Register (CHIPREVID)178
- Boot Configuration Register (BOOTCFG) Field Descriptions178
- Silicon Revision Identification Register (CHIPREVID) Field Descriptions178
  - Kick Registers (KICK0R-KICK1R)179
- Kick 0 Register (KICK0R)179
- Kick 1 Register (KICK1R)179
- Kick 0 Register (KICK0R) Field Descriptions179
- Kick 1 Register (KICK1R) Field Descriptions179
  - Host 1 Configuration Register (HOST1CFG)180
  - Host 1 Configuration Register (HOST1CFG) Field Descriptions180
  - 10.5.7 Interrupt Registers181
- Interrupt Raw Status/Set Register (IRAWSTAT)181
- Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions181
- Interrupt Enable Status/Clear Register (IENSTAT)182
- Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions182
- Interrupt Enable Register (IENSET)183
- Interrupt Enable Clear Register (IENCLR)183
- Interrupt Enable Register (IENSET) Field Descriptions183
- Interrupt Enable Clear Register (IENCLR) Field Descriptions183
  - 10.5.8 Fault Registers184
- End of Interrupt Register (EOI)184
- Fault Address Register (FLTADDRR)184
- End of Interrupt Register (EOI) Field Descriptions184
- Fault Address Register (FLTADDRR) Field Descriptions184
- Fault Status Register (FLTSTAT)185
- Fault Status Register (FLTSTAT) Field Descriptions185
  - Master Priority Registers (MSTPRI0-MSTPRI2)186
- Master Priority 0 Register (MSTPRI0)186
- Master Priority 0 Register (MSTPRI0) Field Descriptions186
- Master Priority 1 Register (MSTPRI1)187
- Master Priority 1 Register (MSTPRI1) Field Descriptions187
- Master Priority 2 Register (MSTPRI2)188
- Master Priority 2 Register (MSTPRI2) Field Descriptions188
  - Pin Multiplexing Control Registers (PINMUX0-PINMUX19)189
- Pin Multiplexing Control 0 Register (PINMUX0)189
- Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions189
- Pin Multiplexing Control 1 Register (PINMUX1)191
- Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions191
- Pin Multiplexing Control 2 Register (PINMUX2)193
- Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions193
- Pin Multiplexing Control 3 Register (PINMUX3)195
- Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions195
- Pin Multiplexing Control 4 Register (PINMUX4)196
- Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions196
- Pin Multiplexing Control 5 Register (PINMUX5)197
- Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions197
- Pin Multiplexing Control 6 Register (PINMUX6)199
- Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions199
- Pin Multiplexing Control 7 Register (PINMUX7)201
- Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions201
- Pin Multiplexing Control 8 Register (PINMUX8)203
- Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions203
- Pin Multiplexing Control 9 Register (PINMUX9)205
- Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions205
- Pin Multiplexing Control 10 Register (PINMUX10)207
- Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions207
- Pin Multiplexing Control 11 Register (PINMUX11)209
- Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions209
- Pin Multiplexing Control 12 Register (PINMUX12)211
- Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions211
- Pin Multiplexing Control 13 Register (PINMUX13)213
- Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions213
- Pin Multiplexing Control 14 Register (PINMUX14)215
- Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions215
- Pin Multiplexing Control 15 Register (PINMUX15)217
- Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions217
- Pin Multiplexing Control 16 Register (PINMUX16)219
- Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions219
- Pin Multiplexing Control 17 Register (PINMUX17)221
- Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions221
- Pin Multiplexing Control 18 Register (PINMUX18)223
- Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions223
- Pin Multiplexing Control 19 Register (PINMUX19)225
- Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions225
  - Suspend Source Register (SUSPSRC)226
- Suspend Source Register (SUSPSRC) Field Descriptions226
  - Chip Signal Register (CHIPSIG)228
- Chip Signal Register (CHIPSIG) Field Descriptions228
  - Chip Signal Clear Register (CHIPSIG_CLR)229
- Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions229
  - Chip Configuration 0 Register (CFGCHIP0)230
- Chip Configuration 0 Register (CFGCHIP0) Field Descriptions230
  - Chip Configuration 1 Register (CFGCHIP1)231
- Chip Configuration 1 Register (CFGCHIP1) Field Descriptions232
  - Chip Configuration 2 Register (CFGCHIP2)235
- Chip Configuration 2 Register (CFGCHIP2) Field Descriptions235
  - Chip Configuration 3 Register (CFGCHIP3)237
- Chip Configuration 3 Register (CFGCHIP3) Field Descriptions237
  - Chip Configuration 4 Register (CFGCHIP4)238
- Chip Configuration 4 Register (CFGCHIP4) Field Descriptions238
11 Boot Considerations239
- 11.1 Introduction240
12 Programmable Real-Time Unit Subsystem (PRUSS)241
13 Enhanced Capture (Ecap) Module243
- 13.1 Introduction244
  - 13.1.1 Purpose of the Peripheral244
  - 13.1.2 Features244
- 13.2 Architecture245
- Multiple Ecap Modules245
  - 13.2.1 Capture and APWM Operating Mode246
- Capture and APWM Modes of Operation246
  - 13.2.2 Capture Mode Description247
- Capture Function Diagram247
- Event Prescale Control248
- Prescale Function Waveforms248
- Continuous/One-Shot Block Diagram249
- Counter and Synchronization Block Diagram250
- Interrupts in Ecap Module252
- PWM Waveform Details of APWM Mode Operation253
  - 13.3 Applications254
    - Absolute Time-Stamp Operation Rising Edge Trigger Example255
- Capture Sequence for Absolute Time-Stamp, Rising Edge Detect255
- ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger256
  - 13.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example257
- Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect257
- ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger258
  - 13.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example259
- Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect259
- ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger260
  - 13.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example261
- Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect261
- ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers262
  - Application of the APWM Mode263
- PWM Waveform Details of APWM Mode Operation263
- ECAP Initialization for APWM Mode264
- Multichannel PWM Example Using 4 Ecap Modules265
- ECAP1 Initialization for Multichannel PWM Generation with Synchronization266
- ECAP2 Initialization for Multichannel PWM Generation with Synchronization266
- ECAP3 Initialization for Multichannel PWM Generation with Synchronization266
- ECAP4 Initialization for Multichannel PWM Generation with Synchronization266
- Multiphase (Channel) Interleaved PWM Example Using 3 Ecap Modules268
- ECAP1 Initialization for Multichannel PWM Generation with Phase Control269
- ECAP2 Initialization for Multichannel PWM Generation with Phase Control269
- ECAP3 Initialization for Multichannel PWM Generation with Phase Control269
  - Registers270
    - Time-Stamp Counter Register (TSCTR)270
    - Control and Status Register Set270
- Time-Stamp Counter Register (TSCTR) Field Descriptions270
  - Counter Phase Control Register (CTRPHS)271
  - Capture 1 Register (CAP1)271
- Counter Phase Control Register (CTRPHS) Field Descriptions271
- Capture 1 Register (CAP1) Field Descriptions271
  - Capture 2 Register (CAP2)272
  - Capture 3 Register (CAP3)272
- Capture 2 Register (CAP2) Field Descriptions272
- Capture 3 Register (CAP3) Field Descriptions272
  - Capture 4 Register (CAP4)273
  - ECAP Control Register 1 (ECCTL1)273
- Capture 4 Register (CAP4) Field Descriptions273
- ECAP Control Register 1 (ECCTL1) Field Descriptions273
  - ECAP Control Register 2 (ECCTL2)275
- ECAP Control Register 2 (ECCTL2) Field Descriptions275
  - ECAP Interrupt Enable Register (ECEINT)276
- ECAP Interrupt Enable Register (ECEINT)277
- ECAP Interrupt Enable Register (ECEINT) Field Descriptions277
  - ECAP Interrupt Flag Register (ECFLG)278
- ECAP Interrupt Flag Register (ECFLG) Field Descriptions278
  - ECAP Interrupt Clear Register (ECCLR)279
- ECAP Interrupt Clear Register (ECCLR) Field Descriptions279
  - ECAP Interrupt Forcing Register (ECFRC)280
- ECAP Interrupt Forcing Register (ECFRC) Field Descriptions280
  - Revision ID Register (REVID)281
- Revision ID Register (REVID) Field Descriptions281
14 Enhanced High-Resolution Pulse-Width Modulator (Ehrpwm)282
- Introduction283
  - 14.1.2 Submodule Overview283
- Multiple Epwm Modules284
- Submodules and Signal Connections for an Epwm Module285
- Epwm Submodules and Critical Internal Signal Interconnects286
  - 14.1.3 Register Mapping287
- Epwm Module Control and Status Registers Grouped by Submodule287
  - 14.2 Architecture288
    - 14.2.1 Overview288
- Submodule Configuration Parameters288
  - 14.2.2 Proper Interrupt Initialization Procedure291
  - 14.2.3 Time-Base (TB) Submodule292
- Time-Base Submodule Block Diagram292
- Time-Base Submodule Signals and Registers293
- Time-Base Submodule Registers293
- Key Time-Base Signals294
- Time-Base Frequency and Period295
- Time-Base Counter Synchronization Scheme 1296
- Time-Base Up-Count Mode Waveforms298
- Time-Base Down-Count Mode Waveforms299
- Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count down on Synchronization Event299
- Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count up on Synchronization Event300
  - 14.2.4 Counter-Compare (CC) Submodule301
- Counter-Compare Submodule301
- Counter-Compare Submodule Signals and Registers301
- Counter-Compare Submodule Registers302
- Counter-Compare Submodule Key Signals302
- Counter-Compare Event Waveforms in Up-Count Mode304
- Counter-Compare Events in Down-Count Mode304
- Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count down on Synchronization Event305
- Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count up on Synchronization Event305
  - 14.2.5 Action-Qualifier (AQ) Submodule306
- Action-Qualifier Submodule306
- Action-Qualifier Submodule Registers306
- Action-Qualifier Submodule Inputs and Outputs307
- Action-Qualifier Submodule Possible Input Events307
- Possible Action-Qualifier Actions for Epwmxa and Epwmxb Outputs308
- Action-Qualifier Event Priority for Up-Down-Count Mode309
- Action-Qualifier Event Priority for Up-Count Mode309
- Action-Qualifier Event Priority for Down-Count Mode309
- Behavior if CMPA/CMPB Is Greater than the Period310
- Up-Down-Count Mode Symmetrical Waveform311
- Up, Single Edge Asymmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb-Active High312
- Epwmx Initialization for313
- Epwmx Run Time Changes for313
- Up, Single Edge Asymmetric Waveform with Independent Modulation on Epwmxa and Epwmxb-Active Low314
- Epwmx Initialization for315
- Epwmx Run Time Changes for315
- Up-Count, Pulse Placement Asymmetric Waveform with Independent Modulation on Epwmxa316
- Epwmx Initialization for317
- Epwmx Run Time Changes for317
- Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Active Low318
- Epwmx Initialization for319
- Epwmx Run Time Changes for319
- Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Complementary320
- Epwmx Initialization for321
- Epwmx Run Time Changes for321
- Up-Down-Count, Dual Edge Asymmetric Waveform, with Independent Modulation on Epwmxa-Active Low322
- Epwmx Initialization for323
- Epwmx Run Time Changes for323
  - 14.2.6 Dead-Band Generator (DB) Submodule324
- Dead-Band Generator Submodule324
- Dead-Band Generator Submodule Registers324
- Configuration Options for the Dead-Band Generator Submodule325
- Classical Dead-Band Operating Modes326
- Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)327
  - 14.2.7 PWM-Chopper (PC) Submodule328
- PWM-Chopper Submodule328
- PWM-Chopper Submodule Registers328
- PWM-Chopper Submodule Signals and Registers329
- Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only330
- PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses330
- PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses331
  - 14.2.8 Trip-Zone (TZ) Submodule332
- Trip-Zone Submodule332
- Trip-Zone Submodule Registers333
- Possible Actions on a Trip Event334
- Trip-Zone Submodule Mode Control Logic335
- Trip-Zone Submodule Interrupt Logic335
  - 14.2.9 Event-Trigger (ET) Submodule336
- Event-Trigger Submodule336
- Event-Trigger Submodule Registers336
- Event-Trigger Submodule Inter-Connectivity to Interrupt Controller337
- Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs337
- Event-Trigger Interrupt Generator339
  - 14.2.10 High-Resolution PWM (HRPWM) Submodule340
- HRPWM System Interface340
- Resolution Calculations for Conventionally Generated PWM341
- Resolution for PWM and HRPWM341
- Operating Logic Using MEP342
- HRPWM Submodule Registers342
- Relationship between MEP Steps, PWM Frequency and Resolution343
- Required PWM Waveform for a Requested Duty344
- CMPA Vs Duty (Left), and [CMPA:CMPAHR] Vs Duty (Right)344
- Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz346
- High % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz346
  - 14.3 Applications to Power Topologies347
    - 14.3.1 Overview of Multiple Modules347
- Simplified Epwm Module347
  - 14.3.2 Key Configuration Capabilities348
- EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave348
  - 14.3.3 Controlling Multiple Buck Converters with Independent Frequencies349
- Control of Four Buck Stages349
- Pwm1 Pwm2 Pwm3 Pwm4349
- Pwm1 ≠ F Pwm2 ≠ F Pwm3 ≠ F349
- Buck Waveforms for (Note: Only Three Bucks Shown Here)350
- Buck Waveforms for350
- EPWM1 Initialization for351
- EPWM2 Initialization for351
- EPWM3 Initialization for351
  - 14.3.4 Controlling Multiple Buck Converters with same Frequencies352
- Control of Four Buck Stages352
- Pwm1 )352
- Pwm2 Pwm1353
- EPWM1 Initialization for354
- EPWM2 Initialization for354
  - 14.3.5 Controlling Multiple Half H-Bridge (HHB) Converters355
- Pwm2 = N × F355
- Pwm1 )355
- Pwm2 Pwm1356
- EPWM1 Initialization for357
- EPWM2 Initialization for357
  - Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)358
- Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control358
- 3-Phase Inverter Waveforms for (Only One Inverter Shown)359
- EPWM1 Initialization for360
- EPWM2 Initialization for360
- EPWM3 Initialization for361
  - 14.3.7 Practical Applications Using Phase Control between PWM Modules362
- Configuring Two PWM Modules for Phase Control362
  - 14.3.8 Controlling a 3-Phase Interleaved DC/DC Converter363
- Timing Waveforms Associated with Phase Control between 2 Modules363
- Control of a 3-Phase Interleaved DC/DC Converter364
- 3-Phase Interleaved DC/DC Converter Waveforms for365
- EPWM1 Initialization for366
- EPWM2 Initialization for366
- EPWM3 Initialization for367
  - 14.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter368
- Pwm2 Pwm1368
- ZVS Full-H Bridge Waveforms369
- EPWM1 Initialization for370
- EPWM2 Initialization for370
  - 14.4 Registers371
    - 14.4.1 Time-Base Submodule Registers371
- Time-Base Control Register (TBCTL)371
- Submodule Registers371
- Time-Base Control Register (TBCTL) Field Descriptions372
- Time-Base Status Register (TBSTS)373
- Time-Base Status Register (TBSTS) Field Descriptions373
- Time-Base Phase Register (TBPHS)374
- Time-Base Counter Register (TBCNT)374
- Time-Base Phase Register (TBPHS) Field Descriptions374
- Time-Base Counter Register (TBCNT) Field Descriptions374
  - 14.4.2 Counter-Compare Submodule Registers375
- Time-Base Period Register (TBPRD)375
- Time-Base Period Register (TBPRD) Field Descriptions375
- Counter-Compare Control Register (CMPCTL)376
- Counter-Compare Control Register (CMPCTL) Field Descriptions376
- Counter-Compare a Register (CMPA)377
- Counter-Compare a Register (CMPA) Field Descriptions377
  - 14.4.3 Action-Qualifier Submodule Registers378
- Counter-Compare B Register (CMPB)378
- Counter-Compare B Register (CMPB) Field Descriptions378
- Action-Qualifier Output a Control Register (AQCTLA)379
- Action-Qualifier Output a Control Register (AQCTLA) Field Descriptions379
- Action-Qualifier Output B Control Register (AQCTLB)380
- Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions380
- Action-Qualifier Software Force Register (AQSFRC)381
- Action-Qualifier Software Force Register (AQSFRC) Field Descriptions381
  - 14.4.4 Dead-Band Generator Submodule Registers382
- Action-Qualifier Continuous Software Force Register (AQCSFRC)382
- Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions382
- Dead-Band Generator Control Register (DBCTL)383
- Dead-Band Generator Control Register (DBCTL) Field Descriptions383
- Dead-Band Generator Rising Edge Delay Register (DBRED)384
- Dead-Band Generator Falling Edge Delay Register (DBFED)384
- Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions384
- Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions384
  - 14.4.5 PWM-Chopper Submodule Register385
- PWM-Chopper Control Register (PCCTL)385
- PWM-Chopper Control Register (PCCTL) Bit Descriptions385
  - 14.4.6 Trip-Zone Submodule Registers386
- Trip-Zone Select Register (TZSEL)386
- Trip-Zone Submodule Select Register (TZSEL) Field Descriptions386
- Trip-Zone Control Register (TZCTL)387
- Trip-Zone Enable Interrupt Register (TZEINT)387
- Trip-Zone Control Register (TZCTL) Field Descriptions387
- Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions387
- Trip-Zone Flag Register (TZFLG)388
- Trip-Zone Flag Register (TZFLG) Field Descriptions388
- Trip-Zone Clear Register (TZCLR)389
- Trip-Zone Force Register (TZFRC)389
- Trip-Zone Clear Register (TZCLR) Field Descriptions389
- Trip-Zone Force Register (TZFRC) Field Descriptions389
  - 14.4.7 Event-Trigger Submodule Registers390
- Event-Trigger Selection Register (ETSEL)390
- Event-Trigger Selection Register (ETSEL) Field Descriptions390
- Event-Trigger Prescale Register (ETPS)391
- Event-Trigger Prescale Register (ETPS) Field Descriptions391
- Event-Trigger Flag Register (ETFLG)392
- Event-Trigger Clear Register (ETCLR)392
- Event-Trigger Flag Register (ETFLG) Field Descriptions392
- Event-Trigger Clear Register (ETCLR) Field Descriptions392
  - 14.4.8 High-Resolution PWM Submodule Registers393
  - Event-Trigger Force Register (ETFRC)393
  - Event-Trigger Force Register (ETFRC) Field Descriptions393
  - Time-Base Phase High-Resolution Register (TBPHSHR)394
  - Counter-Compare a High-Resolution Register (CMPAHR)394
  - Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions394
- Counter-Compare a High-Resolution Register (CMPAHR) Field Descriptions394
- HRPWM Configuration Register (HRCNFG)395
- HRPWM Configuration Register (HRCNFG) Field Descriptions395
15 Enhanced Quadrature Encoder Pulse (Eqep) Module396
- 15.1 Introduction397
- Optical Encoder Disk397
- QEP Encoder Output Signal for Forward/Reverse Movement398
- Index Pulse Example398
  - 15.2 Architecture400
    - 15.2.1 EQEP Inputs400
    - 15.2.2 Functional Description400
- Functional Block Diagram of the Eqep Peripheral401
  - Quadrature Decoder Unit (QDU)402
- Functional Block Diagram of Decoder Unit402
- Quadrature Decoder Truth Table403
- Quadrature Decoder State Machine404
- Quadrature-Clock and Direction Decoding404
  - Position Counter and Control Unit (PCCU)405
- Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh)406
- Position Counter Underflow/Overflow (QPOSMAX = 4)407
- Software Index Marker for 1000-Line Encoder (QEPCTL[IEL] = 1)409
- Strobe Event Latch (QEPCTL[SEL] = 1)410
- Eqep Position-Compare Unit411
- Eqep Position-Compare Event Generation Points412
- Eqep Position-Compare Sync Output Pulse Stretcher412
  - 15.2.5 Eqep Edge Capture Unit413
- Eqep Edge Capture Unit414
- Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)414
- Eqep Edge Capture Unit - Timing Details415
  - 15.2.6 Eqep Watchdog416
- Eqep Watchdog Timer416
  - 15.2.7 Unit Timer Base417
  - 15.2.8 Eqep Interrupt Structure417
- Eqep Unit Time Base417
- EQEP Interrupt Generation417
  - 15.3 Eqep Registers418
- Eqep Position Counter Register (QPOSCNT) Field Descriptions419
- Eqep Position Counter Initialization Register (QPOSINIT) Field Descriptions419
- Eqep Maximum Position Count Register (QPOSMAX) Field Descriptions419
  - Eqep Position-Compare Register (QPOSCMP)420
  - Eqep Index Position Latch Register (QPOSILAT)420
  - Eqep Strobe Position Latch Register (QPOSSLAT)420
- Eqep Position-Compare Register (QPOSCMP) Field Descriptions420
- Eqep Index Position Latch Register (QPOSILAT) Field Descriptions420
- Eqep Strobe Position Latch Register (QPOSSLAT) Field Descriptions420
- Eqep Position Counter Latch Register (QPOSLAT)421
- Eqep Unit Timer Register (QUTMR)421
- Eqep Unit Period Register (QUPRD)421
- Eqep Position Counter Latch Register (QPOSLAT) Field Descriptions421
- Eqep Unit Timer Register (QUTMR) Field Descriptions421
- Eqep Unit Period Register (QUPRD) Field Descriptions421
  - Eqep Watchdog Timer Register (QWDTMR)422
  - Eqep Watchdog Period Register (QWDPRD)422
- Eqep Watchdog Timer Register (QWDTMR) Field Descriptions422
- Eqep Watchdog Period Register (QWDPRD) Field Description422
  - QEP Decoder Control Register (QDECCTL)423
  - Eqep Control Register (QEPCTL)423
- Eqep Decoder Control Register (QDECCTL) Field Descriptions423
- Eqep Control Register (QEPCTL)424
- Eqep Control Register (QEPCTL) Field Descriptions424
  - Eqep Capture Control Register (QCAPCTL)426
- Eqep Capture Control Register (QCAPCTL) Field Descriptions426
  - Eqep Position-Compare Control Register (QPOSCTL)427
- Eqep Position-Compare Control Register (QPOSCTL) Field Descriptions427
  - Eqep Interrupt Enable Register (QEINT)428
- Eqep Interrupt Enable Register (QEINT) Field Descriptions428
  - Eqep Interrupt Flag Register (QFLG)429
- Eqep Interrupt Flag Register (QFLG) Field Descriptions429
  - Eqep Interrupt Clear Register (QCLR)430
- Eqep Interrupt Clear Register (QCLR) Field Descriptions430
  - Eqep Interrupt Force Register (QFRC)432
- Eqep Interrupt Force Register (QFRC) Field Descriptions432
  - Eqep Status Register (QEPSTS)433
- Eqep Status Register (QEPSTS) Field Descriptions433
  - Eqep Capture Timer Register (QCTMR)434
  - Eqep Capture Period Register (QCPRD)434
  - Eqep Capture Timer Latch Register (QCTMRLAT)434
- Eqep Capture Time Register (QCTMR) Field Descriptions434
- Eqep Capture Period Register (QCPRD) Field Descriptions434
- Eqep Capture Timer Latch Register (QCTMRLAT) Field Descriptions434
  - Eqep Capture Period Latch Register (QCPRDLAT)435
  - Eqep Revision ID Register (REVID)435
- Eqep Capture Period Latch Register (QCPRDLAT) Field Descriptions435
- Eqep Revision ID Register (REVID) Field Descriptions435
- SPRUH91D - March 2013 - Revised September 2016436
16 Enhanced Direct Memory Access (EDMA3) Controller436
- 16.1 Introduction437
  - 16.1.1 Overview437
  - 16.1.2 Features437
  - 16.1.3 Functional Block Diagram439
  - 16.1.4 Terminology Used in this Document439
- EDMA3 Controller Block Diagram439
  - 16.2 Architecture441
    - 16.2.1 Functional Overview441
- EDMA3 Channel Controller (EDMA3CC) Block Diagram442
- EDMA3 Transfer Controller (EDMA3TC) Block Diagram443
  - 16.2.2 Types of EDMA3 Transfers444
- Definition of ACNT, BCNT, and CCNT444
- A-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)445
- AB-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)446
  - Parameter RAM (Param)447
- Param Set447
- EDMA3 Channel Parameter Description448
- Dummy and Null Transfer Request451
- Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy Param Set)452
- Linked Transfer Example455
- Link-To-Self Transfer Example456
  - 16.2.4 Initiating a DMA Transfer457
  - 16.2.5 Completion of a DMA Transfer460
- Expected Number of Transfers for Non-Null Transfer460
  - 16.2.6 Event, Channel, and Param Mapping461
- EDMA3 DMA Channel to Param Mapping462
- QDMA Channel to Param Mapping463
  - 16.2.7 EDMA3 Channel Controller Regions464
- Shadow Region Registers464
- Shadow Region Registers465
  - 16.2.8 Chaining EDMA3 Channels466
  - 16.2.9 EDMA3 Interrupts466
- Chain Event Triggers466
- Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping467
- Number of Interrupts468
- Interrupt Diagram469
- Error Interrupt Operation472
  - Event Queue(S)473
  - EDMA3 Transfer Controller (EDMA3TC)475
  - 16.2.12 Event Dataflow478
  - 16.2.13 EDMA3 Prioritization479
  - 16.2.14 EDMA3CC and EDMA3TC Performance and System Considerations481
- Read/Write Command Optimization Rules481
  - EDMA3 Operating Frequency (Clock Control)482
  - 16.2.16 Reset Considerations482
  - 16.2.17 Power Management482
  - 16.2.18 Emulation Considerations483
  - 16.3 Transfer Examples483
    - 16.3.1 Block Move Example483
- Block Move Example Param Configuration484
  - 16.3.2 Subframe Extraction Example485
- Subframe Extraction Example Param Configuration485
  - 16.3.3 Data Sorting Example486
- Data Sorting Example Param Configuration487
  - 16.3.4 Peripheral Servicing Example488
- Servicing Incoming Mcbsp Data Example488
- Servicing Incoming Mcbsp Data Example Param489
- Servicing Peripheral Burst Example490
- Servicing Peripheral Burst Example Param490
- Servicing Continuous Mcbsp Data Example491
- Servicing Continuous Mcbsp Data Example Param492
- Servicing Continuous Mcbsp Data Example Reload Param492
- Ping-Pong Buffering for Mcbsp Data Example495
- Ping-Pong Buffering for Mcbsp Example Param496
- Ping-Pong Buffering for Mcbsp Example Pong Param496
- Ping-Pong Buffering for Mcbsp Example Ping Param497
- Intermediate Transfer Completion Chaining Example499
- Single Large Block Transfer Example499
  - 16.4 Registers500
    - 16.4.1 Parameter RAM (Param) Entries500
- Smaller Packet Data Transfers Example500
- EDMA3 Channel Controller (EDMA3CC) Parameter RAM (Param) Entries500
- Channel Options Parameter (OPT)501
- Channel Options Parameters (OPT) Field Descriptions501
- Channel Source Address Parameter (SRC)503
- A Count/B Count Parameter (A_B_CNT)503
- Channel Source Address Parameter (SRC) Field Descriptions503
- A Count/B Count Parameter (A_B_CNT) Field Descriptions503
- Channel Destination Address Parameter (DST)504
- Source B Index/Destination B Index Parameter (SRC_DST_BIDX)504
- Channel Destination Address Parameter (DST) Field Descriptions504
- Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions504
- Link Address/B Count Reload Parameter (LINK_BCNTRLD)505
- Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions505
- Source C Index/Destination C Index Parameter (SRC_DST_CIDX)506
- C Count Parameter (CCNT)506
- Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions506
- C Count Parameter (CCNT) Field Descriptions506
  - 16.4.2 EDMA3 Channel Controller (EDMA3CC) Registers507
- Revision ID Register (REVID)510
- EDMA3CC Configuration Register (CCCFG)510
- Revision ID Register (REVID) Field Descriptions510
- EDMA3CC Configuration Register (CCCFG) Field Descriptions511
- QDMA Channel N Mapping Register (Qchmapn)512
- QDMA Channel N Mapping Register (Qchmapn) Field Descriptions512
- DMA Channel Queue Number Register N (Dmaqnumn)513
- DMA Channel Queue Number Register N (Dmaqnumn) Field Descriptions513
- Bits in Dmaqnumn513
- QDMA Channel Queue Number Register (QDMAQNUM)514
- QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions514
- Event Missed Register (EMR)515
- Event Missed Register (EMR) Field Descriptions515
- Event Missed Clear Register (EMCR)516
- Event Missed Clear Register (EMCR) Field Descriptions516
- QDMA Event Missed Register (QEMR)517
- QDMA Event Missed Register (QEMR) Field Descriptions517
- QDMA Event Missed Clear Register (QEMCR)518
- QDMA Event Missed Clear Register (QEMCR) Field Descriptions518
- EDMA3CC Error Register (CCERR)519
- EDMA3CC Error Register (CCERR) Field Descriptions519
- EDMA3CC Error Clear Register (CCERRCLR)520
- EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions520
- Error Evaluate Register (EEVAL)521
- Error Evaluate Register (EEVAL) Field Descriptions521
- DMA Region Access Enable Register for Region M (Draem)522
- DMA Region Access Enable Register for Region M (Draem) Field Descriptions522
- QDMA Region Access Enable for Region M (Qraem)523
- QDMA Region Access Enable for Region M (Qraem) Field Descriptions523
- Event Queue Entry Registers (Qxey)524
- Event Queue Entry Registers (Qxey) Field Descriptions524
- Queue N Status Register (Qstatn)525
- Queue N Status Register (Qstatn) Field Descriptions525
- Queue Watermark Threshold a Register (QWMTHRA)526
- Queue Watermark Threshold a Register (QWMTHRA) Field Descriptions526
- EDMA3CC Status Register (CCSTAT)527
- EDMA3CC Status Register (CCSTAT) Field Descriptions527
- Event Register (ER)529
- Event Register (ER) Field Descriptions529
- Event Clear Register (ECR)530
- Event Clear Register (ECR) Field Descriptions530
- Event Set Register (ESR)531
- Event Set Register (ESR) Field Descriptions531
- Chained Event Register (CER)532
- Chained Event Register (CER) Field Descriptions532
- Event Enable Register (EER)533
- Event Enable Register (EER) Field Descriptions533
- Event Enable Clear Register (EECR)534
- Event Enable Set Register (EESR)534
- Event Enable Clear Register (EECR) Field Descriptions534
- Event Enable Set Register (EESR) Field Descriptions534
- Secondary Event Register (SER)535
- Secondary Event Clear Register (SECR)535
- Secondary Event Register (SER) Field Descriptions535
- Secondary Event Clear Register (SECR) Field Descriptions535
- Interrupt Enable Register (IER)536
- Interrupt Enable Register (IER) Field Descriptions536
- Interrupt Enable Clear Register (IECR)537
- Interrupt Enable Set Register (IESR)537
- Interrupt Enable Clear Register (IECR) Field Descriptions537
- Interrupt Enable Set Register (IESR) Field Descriptions537
- Interrupt Pending Register (IPR)538
- Interrupt Pending Register (IPR) Field Descriptions538
- Interrupt Clear Register (ICR)539
- Interrupt Clear Register (ICR) Field Descriptions539
- Interrupt Evaluate Register (IEVAL)540
- Interrupt Evaluate Register (IEVAL) Field Descriptions540
- QDMA Event Register (QER)541
- QDMA Event Register (QER) Field Descriptions541
- QDMA Event Enable Register (QEER)542
- QDMA Event Enable Register (QEER) Field Descriptions542
- QDMA Event Enable Clear Register (QEECR)543
- QDMA Event Enable Set Register (QEESR)543
- QDMA Event Enable Clear Register (QEECR) Field Descriptions543
- QDMA Event Enable Set Register (QEESR) Field Descriptions543
- QDMA Secondary Event Register (QSER)544
- QDMA Secondary Event Register (QSER) Field Descriptions544
- QDMA Secondary Event Clear Register (QSECR)545
- QDMA Secondary Event Clear Register (QSECR) Field Descriptions545
  - 16.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers546
- Revision ID Register (REVID)547
- Revision ID Register (REVID) Field Descriptions547
- EDMA3TC Configuration Register (TCCFG)548
- EDMA3TC Configuration Register (TCCFG) Field Descriptions548
- EDMA3TC Channel Status Register (TCSTAT)549
- EDMA3TC Channel Status Register (TCSTAT) Field Descriptions549
- Error Status Register (ERRSTAT)550
- Error Status Register (ERRSTAT) Field Descriptions550
- Error Enable Register (ERREN)551
- Error Enable Register (ERREN) Field Descriptions551
- Error Clear Register (ERRCLR)552
- Error Clear Register (ERRCLR) Field Descriptions552
- Error Details Register (ERRDET)553
- Error Details Register (ERRDET) Field Descriptions553
- Error Interrupt Command Register (ERRCMD)554
- Error Interrupt Command Register (ERRCMD) Field Descriptions554
- Read Command Rate Register (RDRATE)555
- Read Command Rate Register (RDRATE) Field Descriptions555
- Source Active Options Register (SAOPT)556
- Source Active Options Register (SAOPT) Field Descriptions556
- Source Active Source Address Register (SASRC)557
- Source Active Count Register (SACNT)557
- Source Active Source Address Register (SASRC) Field Descriptions557
- Source Active Count Register (SACNT) Field Descriptions557
- Source Active Destination Address Register (SADST)558
- Source Active B-Index Register (SABIDX)558
- Source Active Destination Address Register (SADST) Field Descriptions558
- Source Active B-Index Register (SABIDX) Field Descriptions558
- Source Active Memory Protection Proxy Register (SAMPPRXY)559
- Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions559
- Source Active Count Reload Register (SACNTRLD)560
- Source Active Source Address B-Reference Register (SASRCBREF)560
- Source Active Count Reload Register (SACNTRLD) Field Descriptions560
- Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions560
- Source Active Destination Address B-Reference Register (SADSTBREF)561
- Destination FIFO Set Count Reload Register (DFCNTRLD)561
- Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions561
- Destination FIFO Set Count Reload Register (DFCNTRLD) Field Descriptions561
- Destination FIFO Set Source Address B-Reference Register (DFSRCBREF)562
- Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF)562
- Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions562
- Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions562
- Destination FIFO Options Register N (Dfoptn)563
- Destination FIFO Options Register N (Dfoptn) Field Descriptions563
- Destination FIFO Source Address Register N (Dfsrcn)564
- Destination FIFO Count Register N (Dfcntn)564
- Destination FIFO Source Address Register N (Dfsrcn) Field Descriptions564
- Destination FIFO Count Register N (Dfcntn) Field Descriptions564
- Destination FIFO Destination Address Register N (Dfdstn)565
- Destination FIFO B-Index Register N (Dfbidxn)565
- Destination FIFO Destination Address Register N (Dfdstn) Field Descriptions565
- Destination FIFO B-Index Register N (Dfbidxn) Field Descriptions565
- Destination FIFO Memory Protection Proxy Register N (Dfmpprxyn)566
- Destination FIFO Memory Protection Proxy Register N (Dfmpprxyn) Field Descriptions566
  - 16.5 Tips567
    - 16.5.1 Debug Checklist567
- Debug List567
  - 16.5.2 Miscellaneous Programming/Debug Tips568
  - 16.6 Setting up a Transfer569
17 EMAC/MDIO Module570
- 17.1 Introduction571
  - 17.1.1 Purpose of the Peripheral571
  - 17.1.2 Features571
  - 17.1.3 Functional Block Diagram572
- EMAC and MDIO Block Diagram572
  - 17.1.4 Industry Standard(S) Compliance Statement573
  - 17.1.5 Terminology573
  - 17.2 Architecture574
- Ethernet Configuration-MII Connections575
- EMAC and MDIO Signals for MII Interface576
- Ethernet Configuration-RMII Connections577
- EMAC and MDIO Signals for RMII Interface577
  - 17.2.4 Ethernet Protocol Overview578
- Ethernet Frame Format578
- Ethernet Frame Description578
  - 17.2.5 Programming Interface579
- Basic Descriptor Format579
- Typical Descriptor Linked List580
- Basic Descriptor Description580
- Transmit Buffer Descriptor Format583
- Receive Buffer Descriptor Format586
  - 17.2.6 EMAC Control Module590
- EMAC Control Module Block Diagram590
  - 17.2.7 MDIO Module591
- MDIO Module Block Diagram592
  - 17.2.8 EMAC Module596
- EMAC Module Block Diagram596
  - 17.2.9 MAC Interface598
  - 17.2.10 Packet Receive Operation602
- Receive Frame Treatment Summary605
- Middle of Frame Overrun Treatment606
  - 17.2.11 Packet Transmit Operation607
  - 17.2.12 Receive and Transmit Latency608
  - 17.2.13 Transfer Node Priority608
  - 17.2.14 Reset Considerations609
  - 17.2.15 Initialization610
  - 17.2.16 Interrupt Support612
  - 17.2.17 Power Management616
  - 17.2.18 Emulation Considerations616
- Emulation Control616
  - 17.3 Registers617
    - 17.3.1 EMAC Control Module Registers617
- EMAC Control Module Revision ID Register (REVID)618
- EMAC Control Module Revision ID Register (REVID) Field Descriptions618
- EMAC Control Module Software Reset Register (SOFTRESET)619
- EMAC Control Module Interrupt Control Register (INTCONTROL)620
- EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (Cnrxthreshen)621
- EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (Cnrxen)622
- EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (Cntxen)623
- EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (Cnmiscen)624
- EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register (Cnrxthreshstat)625
- EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (Cnrxstat)626
- EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (Cntxstat)627
- EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (Cnmiscstat)628
- EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (Cnrximax)629
- EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (Cntximax)630
  - 17.3.2 MDIO Registers631
- MDIO Revision ID Register (REVID)631
- Management Data Input/Output (MDIO) Registers631
- MDIO Revision ID Register (REVID) Field Descriptions631
- MDIO Control Register (CONTROL)632
- MDIO Control Register (CONTROL) Field Descriptions632
- PHY Acknowledge Status Register (ALIVE)633
- PHY Link Status Register (LINK)633
- PHY Acknowledge Status Register (ALIVE) Field Descriptions633
- PHY Link Status Register (LINK) Field Descriptions633
- MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)634
- MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions634
- MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)635
- MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions635
- MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)636
- MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions636
- MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)637
- MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions637
- MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)638
- MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions638
- MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)639
- MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field639
  - Descriptions639
- MDIO User Access Register 0 (USERACCESS0)640
- MDIO User Access Register 0 (USERACCESS0) Field Descriptions640
- MDIO User PHY Select Register 0 (USERPHYSEL0)641
- MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions641
- MDIO User Access Register 1 (USERACCESS1)642
- MDIO User Access Register 1 (USERACCESS1) Field Descriptions642
- MDIO User PHY Select Register 1 (USERPHYSEL1)643
- MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions643
  - 17.3.3 EMAC Module Registers644
- Ethernet Media Access Controller (EMAC) Registers644
- Transmit Revision ID Register (TXREVID)647
- Transmit Control Register (TXCONTROL)647
- Transmit Revision ID Register (TXREVID) Field Descriptions647
- Transmit Control Register (TXCONTROL) Field Descriptions647
- Transmit Teardown Register (TXTEARDOWN)648
- Transmit Teardown Register (TXTEARDOWN) Field Descriptions648
- Receive Revision ID Register (RXREVID)649
- Receive Control Register (RXCONTROL)649
- Receive Revision ID Register (RXREVID) Field Descriptions649
- Receive Control Register (RXCONTROL) Field Descriptions649
- Receive Teardown Register (RXTEARDOWN)650
- Receive Teardown Register (RXTEARDOWN) Field Descriptions650
- Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)651
- Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions651
- Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)652
- Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions652
- Transmit Interrupt Mask Set Register (TXINTMASKSET)653
- Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions653
- Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)654
- Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions654
- MAC Input Vector Register (MACINVECTOR)655
- MAC Input Vector Register (MACINVECTOR) Field Descriptions655
- MAC End of Interrupt Vector Register (MACEOIVECTOR)656
- MAC End of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions656
- Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)657
- Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions657
- Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)658
- Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions658
- Receive Interrupt Mask Set Register (RXINTMASKSET)659
- Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions659
- Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)660
- Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions660
- MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)661
- MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)661
- MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions661
- MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions661
- MAC Interrupt Mask Set Register (MACINTMASKSET)662
- MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)662
- MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions662
- MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions662
- Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)663
- Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions663
- Receive Unicast Enable Set Register (RXUNICASTSET)666
- Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions666
- Receive Unicast Clear Register (RXUNICASTCLEAR)667
- Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions667
- Receive Maximum Length Register (RXMAXLEN)668
- Receive Buffer Offset Register (RXBUFFEROFFSET)668
- Receive Maximum Length Register (RXMAXLEN) Field Descriptions668
- Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions668
- Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)669
- Receive Channel N Flow Control Threshold Register (Rxnflowthresh)669
- Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions669
- Receive Channel N Flow Control Threshold Register (Rxnflowthresh) Field Descriptions669
- Receive Channel N Free Buffer Count Register (Rxnfreebuffer)670
- Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions670
- MAC Control Register (MACCONTROL)671
- MAC Control Register (MACCONTROL) Field Descriptions671
- MAC Status Register (MACSTATUS)673
- MAC Status Register (MACSTATUS) Field Descriptions673
- Emulation Control Register (EMCONTROL)675
- FIFO Control Register (FIFOCONTROL)675
- Emulation Control Register (EMCONTROL) Field Descriptions675
- FIFO Control Register (FIFOCONTROL) Field Descriptions675
- MAC Configuration Register (MACCONFIG)676
- Soft Reset Register (SOFTRESET)676
- MAC Configuration Register (MACCONFIG) Field Descriptions676
- Soft Reset Register (SOFTRESET) Field Descriptions676
- MAC Source Address Low Bytes Register (MACSRCADDRLO)677
- MAC Source Address High Bytes Register (MACSRCADDRHI)677
- MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions677
- MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions677
- MAC Hash Address Register 1 (MACHASH1)678
- MAC Hash Address Register 2 (MACHASH2)678
- MAC Hash Address Register 1 (MACHASH1) Field Descriptions678
- MAC Hash Address Register 2 (MACHASH2) Field Descriptions678
- Back off Random Number Generator Test Register (BOFFTEST)679
- Transmit Pacing Algorithm Test Register (TPACETEST)679
- Back off Test Register (BOFFTEST) Field Descriptions679
- Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions679
- Receive Pause Timer Register (RXPAUSE)680
- Transmit Pause Timer Register (TXPAUSE)680
- Receive Pause Timer Register (RXPAUSE) Field Descriptions680
- Transmit Pause Timer Register (TXPAUSE) Field Descriptions680
- MAC Address Low Bytes Register (MACADDRLO)681
- MAC Address Low Bytes Register (MACADDRLO) Field Descriptions681
- MAC Address High Bytes Register (MACADDRHI)682
- MAC Index Register (MACINDEX)682
- MAC Address High Bytes Register (MACADDRHI) Field Descriptions682
- MAC Index Register (MACINDEX) Field Descriptions682
- Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp)683
- Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp)683
- Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp) Field Descriptions683
- Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp) Field Descriptions683
- Transmit Channel N Completion Pointer Register (Txncp)684
- Receive Channel N Completion Pointer Register (Rxncp)684
- Transmit Channel N Completion Pointer Register (Txncp) Field Descriptions684
- Receive Channel N Completion Pointer Register (Rxncp) Field Descriptions684
- Statistics Register685
18 External Memory Interface a (EMIFA)694
- 18.1 Introduction695
  - 18.1.1 Purpose of the Peripheral695
  - 18.1.2 Features695
  - 18.1.3 Functional Block Diagram695
- 18.2 Architecture695
- EMIFA Functional Block Diagram695
  - 18.2.1 Clock Control696
  - 18.2.2 EMIFA Requests696
  - 18.2.3 Pin Descriptions696
- EMIFA Pins Used to Access both SDRAM and Asynchronous Memories696
- EMIFA Pins Specific to SDRAM697
- EMIFA Pins Specific to Asynchronous Memory697
  - 18.2.4 SDRAM Controller and Interface698
- EMIFA SDRAM Commands698
- Truth Table for SDRAM Commands698
- Timing Waveform of SDRAM PRE Command699
- EMIFA to 2M × 16 × 4 Bank SDRAM Interface700
- EMIFA to 512K × 16 × 2 Bank SDRAM Interface700
- 16-Bit EMIFA Address Pin Connections700
- Description of the SDRAM Configuration Register (SDCR)701
- Description of the SDRAM Refresh Control Register (SDRCR)701
- Description of the SDRAM Timing Register (SDTIMR)702
- Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR)702
- SDRAM LOAD MODE REGISTER Command703
- Refresh Urgency Levels704
- Timing Waveform for Basic SDRAM Read Operation707
- Timing Waveform for Basic SDRAM Write Operation708
- Mapping from Logical Address to EMIFA Pins for 16-Bit SDRAM709
  - 18.2.5 Asynchronous Controller and Interface710
- EMIFA Asynchronous Interface710
- Normal Mode Vs. Select Strobe Mode710
- EMIFA to 8-Bit/16-Bit Memory Interface711
- Common Asynchronous Interface711
- Description of the Asynchronous M Configuration Register (Cencfg)712
- Description of the Asynchronous Wait Cycle Configuration Register (AWCC)713
- Description of the EMIFA Interrupt Mask Set Register (INTMSKSET)715
- Description of the EMIFA Interrupt Mast Clear Register (INTMSKCLR)715
- Asynchronous Read Operation in Normal Mode715
- Timing Waveform of an Asynchronous Read Cycle in Normal Mode716
- Asynchronous Write Operation in Normal Mode717
- Timing Waveform of an Asynchronous Write Cycle in Normal Mode718
- Asynchronous Read Operation in Select Strobe Mode719
- Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode720
- Asynchronous Write Operation in Select Strobe Mode721
- Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode722
- Description of the NAND Flash Control Register (NANDFCR)723
- EMIFA to NAND Flash Interface724
- ECC Value for 8-Bit NAND Flash726
  - 18.2.6 Data Bus Parking729
  - 18.2.7 Reset and Initialization Considerations729
- EMIFA Reset Block Diagram729
- Reset Sources729
  - 18.2.8 Interrupt Support730
  - 18.2.9 EDMA Event Support731
  - 18.2.10 Pin Multiplexing731
  - 18.2.11 Memory Map731
- Interrupt Monitor and Control Bit Fields731
  - 18.2.12 Priority and Arbitration732
  - 18.2.13 System Considerations733
  - 18.2.14 Power Management734
- EMIFA PSC Block Diagram734
  - 18.2.15 Emulation Considerations735
  - 18.3 Example Configuration736
- SR Field Value for the EMIFA to K4S641632H-TC(L)70 Interface736
- Example Configuration Interface737
- SDRAM Timing Register (SDTIMR)738
- SDTIMR Field Calculations for the EMIFA to K4S641632H-TC(L)70 Interface738
- SDRAM Self Refresh Exit Timing Register (SDSRETR)739
- SDRAM Refresh Control Register (SDRCR)739
- RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface739
- SDRAM Configuration Register (SDCR)740
- SDCR Field Values for the EMIFA to K4S641632H-TC(L)70 Interface740
- EMIFA Input Timing Requirements741
- ASRAM Output Timing Characteristics741
- ASRAM Input Timing Requirement for a Read741
- Timing Waveform of an ASRAM Read742
- ASRAM Input Timing Requirements for a Write742
- Timing Waveform of an ASRAM Write743
- ASRAM Timing Requirements with PCB Delays744
- Timing Waveform of an ASRAM Read with PCB Delays745
- Timing Waveform of an ASRAM Write with PCB Delays746
- EMIFA Timing Requirements for TC5516100FT-12 Example747
- ASRAM Timing Requirements for TC5516100FT-12 Example747
- Measured PCB Delays for TC5516100FT-12 Example747
- Configuring CE3CFG for TC5516100FT-12 Example749
- Recommended Margins749
- EMIFA Read Timing Requirements750
- NAND Flash Read Timing Requirements750
- Timing Waveform of a NAND Flash Read751
- NAND Flash Write Timing Requirements752
- Timing Waveform of a NAND Flash Command Write753
- Timing Waveform of a NAND Flash Address Write753
- Timing Waveform of a NAND Flash Data Write754
- EMIFA Timing Requirements for HY27UA081G1M Example755
- NAND Flash Timing Requirements for HY27UA081G1M Example755
- Configuring CE2CFG for HY27UA081G1M Example757
- Configuring NANDFCR for HY27UA081G1M Example757
- External Memory Interface (EMIFA) Registers758
- Module ID Register (MIDR)759
- Asynchronous Wait Cycle Configuration Register (AWCCR)759
- Module ID Register (MIDR) Field Descriptions759
- Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions760
- SDRAM Configuration Register (SDCR)761
- SDRAM Configuration Register (SDCR) Field Descriptions761
- SDRAM Refresh Control Register (SDRCR)763
- SDRAM Refresh Control Register (SDRCR) Field Descriptions763
- Asynchronous N Configuration Register (Cencfg)764
- Asynchronous N Configuration Register (Cencfg) Field Descriptions764
- SDRAM Timing Register (SDTIMR)766
- SDRAM Timing Register (SDTIMR) Field Descriptions766
- SDRAM Self Refresh Exit Timing Register (SDSRETR)767
- SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions767
- EMIFA Interrupt Raw Register (INTRAW)768
- EMIFA Interrupt Raw Register (INTRAW) Field Descriptions768
- EMIFA Interrupt Mask Register (INTMSK)769
- EMIFA Interrupt Mask Register (INTMSK) Field Descriptions769
- EMIFA Interrupt Mask Set Register (INTMSKSET)770
- EMIFA Interrupt Mask Set Register (INTMSKSET) Field Descriptions770
- EMIFA Interrupt Mask Clear Register (INTMSKCLR)771
- EMIFA Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions771
- NAND Flash Control Register (NANDFCR)772
- NAND Flash Control Register (NANDFCR) Field Descriptions772
- NAND Flash Status Register (NANDFSR)774
- NAND Flash Status Register (NANDFSR) Field Descriptions774
- NAND Flash N ECC Register (Nandfnecc)775
- NAND Flash N ECC Register (Nandfnecc) Field Descriptions775
- NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD)776
- NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions776
- NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1)777
- NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2)777
- NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) Field Descriptions777
- NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) Field Descriptions777
- NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3)778
- NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4)778
- NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) Field Descriptions778
- NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) Field Descriptions778
- NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1)779
- NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2)779
- NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions779
- NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions779
- NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1)780
- NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2)780
- NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions780
- NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions780
19 External Memory Interface B (EMIFB)781
1 Overview782
- EMIFB Functional Block Diagram782
  - Introduction782
- EMIF Pins Used to Access SDRAM783
- Architecture783
- EMIF SDRAM Commands784
  - Pin Multiplexing784
- Timing Waveform of SDRAM PRE Command785
- Truth Table for SDRAM Commands785
- EMIFB to 2M × 16 × 4 Bank SDRAM Interface786
- EMIFB to 2M × 32 × 4 Bank SDRAM Interface786
- EMIFB to Dual 4M × 16 × 4 Bank SDRAM Interface787
- Example of 32-Bit EMIFB Address Pin Connections787
- Example of 16-Bit EMIFB Address Pin Connections788
- Description of the SDRAM Configuration Register (SDCFG)788
- Description of the SDRAM Refresh Control Register (SDRFC)789
- Description of the SDRAM Timing 1 Register (SDTIM1)789
- Description of the SDRAM Timing 2 Register (SDTIM2)789
- Description of the SDRAM Configuration 2 Register (SDCFG2)790
- Mobile SDRAM LOAD MODE REGISTER Command790
- Sdram/Mobile SDRAM LOAD MODE REGISTER Command791
- Refresh Urgency Levels792
- Timing Waveform for Basic SDRAM Read Operation795
- Timing Waveform for Basic SDRAM Write Operation796
- Example Mapping from Logical Address to EMIFB Pins for 32-Bit SDRAM797
- Example Mapping from Logical Address to EMIFB Pins for 16-Bit SDRAM798
- Example Mapping from Logical Address to EMIFB Pins for Mobile SDRAM798
- EMIFB Memory Controller FIFO Block Diagram799
- SDRAM Memory Controller FIFO Description799
- EMIFB Memory Controller Reset Block Diagram802
- Reset Sources802
  - Reset and Initialization Considerations802
- EMIFB Memory Controller Power and Sleep Controller Diagram803
- Power Management803
- Emulation Considerations805
- Connecting EMIFB Memory Controller for 32-Bit Connection806
- Connecting EMIFB Memory Controller for 16-Bit Connection806
- SDCFG Configuration807
- SDRFC Configuration807
- SDTIM1 Configuration808
- SDTIM2 Configuration808
- Revision ID Register (REVID)809
- EMIFB Base Controller Registers809
- Revision ID Register (REVID) Field Descriptions809
- SDRAM Configuration Register (SDCFG)810
- SDRAM Configuration Register (SDCFG) Field Descriptions810
- SDRAM Refresh Control Register (SDRFC)812
- SDRAM Refresh Control Register (SDRFC) Field Descriptions812
- SDRAM Timing 1 Register (SDTIM1)813
- SDRAM Timing 1 Register (SDTIM1) Field Descriptions813
- SDRAM Timing 2 Register (SDTIM2)814
- SDRAM Timing 2 Register (SDTIM2) Field Descriptions814
- SDRAM Configuration 2 Register (SDCFG2)815
- SDRAM Configuration 2 Register (SDCFG2) Field Description815
- Peripheral Bus Burst Priority Register (BPRIO)816
- Peripheral Bus Burst Priority Register (BPRIO) Field Descriptions816
- Performance Counter 1 Register (PC1)817
- Performance Counter 2 Register (PC2)817
- Performance Counter 1 Register (PC1) Field Descriptions817
- Performance Counter 2 Register (PC2) Field Descriptions817
- Performance Counter Configuration Register (PCC)818
- Performance Counter Configuration Register (PCC) Field Descriptions818
- Performance Counter Filter Configuration819
- Performance Counter Master Region Select Register (PCMRS)820
- Performance Counter Master Region Select Register (PCMRS) Field Descriptions820
- Performance Counter Time Register (PCT)821
- Interrupt Raw Register (IRR)821
- Performance Counter Time Register (PCT) Field Description821
- Interrupt Raw Register (IRR) Field Descriptions821
- Interrupt Mask Register (IMR)822
- Interrupt Mask Register (IMR) Field Descriptions822
- Interrupt Mask Set Register (IMSR)823
- Interrupt Mask Clear Register (IMCR)823
- Interrupt Mask Set Register (IMSR) Field Descriptions823
- Interrupt Mask Clear Register (IMCR) Field Descriptions823
20 General-Purpose Input/Output (GPIO)824
3 System Interconnect825
- Introduction825
- GPIO Block Diagram826
  - Architecture826
- GPIO Register Bits and Banks Associated with GPIO Signals827
  - GPIO Register Structure827
  - Using a GPIO Signal as an Output830
  - Using a GPIO Signal as an Input831
    - Initialization832
    - EDMA Event Support833
- GPIO Registers834
- Revision ID Register (REVID)835
- Revision ID Register (REVID) Field Descriptions835
- GPIO Interrupt Per-Bank Enable Register (BINTEN)836
- GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions836
- GPIO Banks 0 and 1 Direction Register (DIR01)837
- GPIO Banks 2 and 3 Direction Register (DIR23)837
- GPIO Banks 4 and 5 Direction Register (DIR45)837
- GPIO Banks 6 and 7 Direction Register (DIR67)837
  - GPIO Direction Registers (Dirn)837
- GPIO Bank 8 Direction Register (DIR8)838
- GPIO Direction Register (Dirn) Field Descriptions838
- GPIO Banks 0 and 1 Output Data Register (OUT_DATA01)839
- GPIO Banks 2 and 3 Output Data Register (OUT_DATA23)839
- GPIO Banks 4 and 5 Output Data Register (OUT_DATA45)839
- GPIO Banks 6 and 7 Output Data Register (OUT_DATA67)839
  - GPIO Output Data Registers (Out_Datan)839
- GPIO Bank 8 Output Data Register (OUT_DATA8)840
- GPIO Output Data Register (Out_Datan) Field Descriptions840
- GPIO Banks 0 and 1 Set Data Register (SET_DATA01)841
- GPIO Banks 2 and 3 Set Data Register (SET_DATA23)841
- GPIO Banks 4 and 5 Set Data Register (SET_DATA45)841
- GPIO Banks 6 and 7 Set Data Register (SET_DATA67)841
  - GPIO Set Data Registers (Set_Datan)841
  - GPIO Bank 8 Set Data Register (SET_DATA8)842
- GPIO Set Data Register (Set_Datan) Field Descriptions842
- GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01)843
- GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23)843
- GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45)843
- GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67)843
  - GPIO Clear Data Registers (Clr_Datan)843
- GPIO Bank 8 Clear Data Register (CLR_DATA8)844
- GPIO Clear Data Register (Clr_Datan) Field Descriptions844
- GPIO Banks 0 and 1 Input Data Register (IN_DATA01)845
- GPIO Banks 2 and 3 Input Data Register (IN_DATA23)845
- GPIO Banks 4 and 5 Input Data Register (IN_DATA45)845
- GPIO Banks 6 and 7 Input Data Register (IN_DATA67)845
  - GPIO Input Data Registers (In_Datan)845
- GPIO Bank 8 Input Data Register (IN_DATA8)846
- GPIO Input Data Register (In_Datan) Field Descriptions846
- GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01)847
- GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23)847
- GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45)847
- GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67)847
  - GPIO Set Rising Edge Interrupt Registers (Set_Ris_Trign)847
- GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8)848
- GPIO Set Rising Edge Trigger Interrupt Register (Set_Ris_Trign) Field Descriptions848
- GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01)849
- GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23)849
- GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45)849
- GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67)849
  - GPIO Clear Rising Edge Interrupt Registers (Clr_Ris_Trign)849
- GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8)850
- GPIO Clear Rising Edge Interrupt Register (Clr_Ris_Trign) Field Descriptions850
- GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01)851
- GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23)851
- GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45)851
- GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67)851
  - GPIO Set Falling Edge Interrupt Registers (Set_Fal_Trign)851
- GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8)852
- GPIO Set Falling Edge Trigger Interrupt Register (Set_Fal_Trign) Field Descriptions852
- GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01)853
- GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23)853
- GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45)853
- GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67)853
  - GPIO Clear Falling Edge Interrupt Registers (Clr_Fal_Trign)853
- GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8)854
- GPIO Clear Falling Edge Interrupt Register (Clr_Fal_Trign) Field Descriptions854
- GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01)855
- GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23)855
- GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45)855
- GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67)855
  - GPIO Interrupt Status Registers (Intstatn)855
- GPIO Bank 8 Interrupt Status Register (INTSTAT8)856
- GPIO Interrupt Status Register (Intstatn) Field Descriptions856
21 Host Port Interface (HPI)857
- Introduction858
- HPI Block Diagram859
  - Functional Block Diagram859
  - Industry Standard(S) Compliance Statement860
- HPI Pins861
- Architecture861
- Value on Optional Pins When Configured as General-Purpose I/O862
  - Pin Multiplexing and General-Purpose I/O Control Blocks862
    - Protocol Description863
- Example of Host-Processor Signal Connections864
- HPI Strobe and Select Logic866
- Options for Connecting Host and HPI Data Strobe Pins866
- Access Types Selectable with the UHPI_HCNTL Signals867
- Cycle Types Selectable with the UHPI_HCNTL and UHPI_HR/W Signals867
- Multiplexed-Mode Host Read Cycle868
- Multiplexed-Mode Host Write Cycle869
- Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write)870
- UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode871
- UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode871
  - Cycle Followed by Nonautoincrement HPID Read Cycle)871
- UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Autoincrement HPID Read Cycles)871
- UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode872
- UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 1: no Autoincrementing)872
- UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode872
  - Autoincrementing Selected, FIFO Empty before Write)872
  - Autoincrementing Selected, FIFO Not Empty before Write)873
- Fifos in the HPI874
  - Reset Considerations878
- Host-To-CPU Interrupt State Diagram879
  - Interrupt Support879
- CPU-To-Host Interrupt State Diagram880
- EDMA Event Support880
- HPI Registers881
  - Emulation Considerations881
- Revision Identification Register (REVID)882
- Power and Emulation Management Register (PWREMU_MGMT)882
- Revision Identification Register (REVID) Field Descriptions882
- Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions882
- GPIO Enable Register (GPIO_EN)883
- GPIO Enable Register (GPIO_EN) Field Descriptions883
- GPIO Direction 1 Register (GPIO_DIR1)884
- GPIO Data 1 Register (GPIO_DAT1)884
- GPIO Direction 1 Register (GPIO_DIR1) Field Descriptions884
- GPIO Data 1 Register (GPIO_DAT1) Field Descriptions884
- GPIO Direction 2 Register (GPIO_DIR2)885
- GPIO Direction 2 Register (GPIO_DIR2) Field Descriptions885
- GPIO Data 2 Register (GPIO_DAT2)886
- GPIO Data 2 Register (GPIO_DAT2) Field Descriptions886
- Host Port Interface Control Register (HPIC)-Host Access Permissions887
- Host Port Interface Control Register (HPIC)-CPU Access Permissions887
- Host Port Interface Control Register (HPIC) Field Descriptions888
- Host Port Interface Write Address Register (HPIAW)889
- Host Port Interface Read Address Register (HPIAR)889
- Host Port Interface Write Address Register (HPIAW) Field Descriptions889
- Host Port Interface Read Address Register (HPIAR) Field Descriptions889
22 Inter-Integrated Circuit (I2C) Module890
- Introduction891
- I2C Peripheral Block Diagram892
  - Functional Block Diagram892
- Multiple I2C Modules Connected893
- Architecture893
- Clocking Diagram for the I2C Peripheral894
  - Clock Generation894
- Synchronization of Two I2C Clock Generators During Arbitration895
- Bit Transfer on the I2C-Bus896
- I2C Peripheral START and STOP Conditions896
- I2C Peripheral Data Transfer897
- I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR)897
  - Serial Data Formats897
- I2C Peripheral 10-Bit Addressing Format with Master-Transmitter Writing to Slave-Receiver (FDF = 0, XA = 1 in ICMDR)898
- I2C Peripheral Free Data Format (FDF = 1 in ICMDR)898
- I2C Peripheral 7-Bit Addressing Format with Repeated START Condition (FDF = 0, XA = 0 in ICMDR)898
- Operating Modes of the I2C Peripheral899
- Ways to Generate a NACK Bit900
  - NACK Bit Generation900
- Arbitration Procedure between Two Master-Transmitters901
  - Reset Considerations902
  - Interrupt Support903
- Descriptions of the I2C Interrupt Events904
  - DMA Events Generated by the I2C Peripheral904
- Inter-Integrated Circuit (I2C) Registers905
- I2C Own Address Register (ICOAR)906
- I2C Own Address Register (ICOAR) Field Descriptions906
- I2C Interrupt Mask Register (ICIMR)907
- I2C Interrupt Mask Register (ICIMR) Field Descriptions907
- I2C Interrupt Status Register (ICSTR)908
- I2C Interrupt Status Register (ICSTR) Field Descriptions908
- I2C Clock Low-Time Divider Register (ICCLKL)911
- I2C Clock High-Time Divider Register (ICCLKH)911
- I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions911
- I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions911
  - I2C Clock Divider Registers (ICCLKL and ICCLKH)911
- I2C Data Count Register (ICCNT)912
- I2C Data Count Register (ICCNT) Field Descriptions912
- I2C Data Receive Register (ICDRR)913
- I2C Data Receive Register (ICDRR) Field Descriptions913
- I2C Slave Address Register (ICSAR)914
- I2C Slave Address Register (ICSAR) Field Descriptions914
- I2C Data Transmit Register (ICDXR)915
- I2C Data Transmit Register (ICDXR) Field Descriptions915
- I2C Mode Register (ICMDR)916
- I2C Mode Register (ICMDR) Field Descriptions916
- Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits918
- How the MST and FDF Bits Affect the Role of TRX Bit918
- Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit919
- I2C Interrupt Vector Register (ICIVR)920
- I2C Interrupt Vector Register (ICIVR) Field Descriptions920
- I2C Extended Mode Register (ICEMDR)921
- I2C Extended Mode Register (ICEMDR) Field Descriptions921
- I2C Prescaler Register (ICPSC)922
- I2C Prescaler Register (ICPSC) Field Descriptions922
- I2C Revision Identification Register 1 (REVID1)923
- I2C Revision Identification Register 2 (REVID2)923
- I2C Revision Identification Register 1 (REVID1) Field Descriptions923
- I2C Revision Identification Register 2 (REVID2) Field Descriptions923
- I2C DMA Control Register (ICDMAC)924
- I2C DMA Control Register (ICDMAC) Field Descriptions924
- I2C Pin Function Register (ICPFUNC)925
- I2C Pin Function Register (ICPFUNC) Field Descriptions925
- I2C Pin Direction Register (ICPDIR)926
- I2C Pin Direction Register (ICPDIR) Field Descriptions926
- I2C Pin Data in Register (ICPDIN)927
- I2C Pin Data in Register (ICPDIN) Field Descriptions927
- I2C Pin Data out Register (ICPDOUT)928
- I2C Pin Data out Register (ICPDOUT) Field Descriptions928
- I2C Pin Data Set Register (ICPDSET)929
- I2C Pin Data Set Register (ICPDSET) Field Descriptions929
- I2C Pin Data Clear Register (ICPDCLR)930
- I2C Pin Data Clear Register (ICPDCLR) Field Descriptions930
23 Liquid Crystal Display Controller (LCDC)931
- LCD Controller932
- Introduction932
- Input and Output Clocks933
  - Features933
- LCD External I/O Signals935
- Register Configuration for DMA Engine Programming936
  - LIDD Controller937
- LIDD I/O Name Map938
- Operation Modes Supported by Raster Controller939
- Logical Data Path for Raster Controller940
- Frame Buffer Structure941
- Bits-Per-Pixel Encoding for Palette Entry 0 Buffer941
- 16-Entry Palette/Buffer Format (1, 2, 4, 12, 16 BPP)942
- Frame Buffer Size According to BPP942
- 256-Entry Palette/Buffer Format (8 BPP)943
- 16-BPP Data Memory Organization (TFT Mode Only)-Little Endian943
- 12-BPP Data Memory Organization-Little Endian944
- 8-BPP Data Memory Organization944
- 2-BPP Data Memory Organization945
- Color/Grayscale Intensities and Modulation Rates946
- Number of Colors/Shades of Gray Available on Screen946
- Monochrome and Color Output947
- Raster Mode Display Format948
- LCD Revision Identification Register (REVID)949
- LCD Controller (LCDC) Registers949
- LCD Revision Identification Register (REVID) Field Descriptions949
- LCD Control Register (LCD_CTRL)950
- LCD Control Register (LCD_CTRL) Field Descriptions950
- Pixel Clock Frequency Programming Limitations951
- LCD Status Register (LCD_STAT)952
- LCD Status Register (LCD_STAT) Field Descriptions952
- LCD LIDD Control Register (LIDD_CTRL)955
- LCD LIDD Control Register (LIDD_CTRL) Field Descriptions955
- LCD LIDD Csn Configuration Register (Lidd_Csn_Conf)957
- LCD LIDD Csn Configuration Register (Lidd_Csn_Conf) Field Descriptions957
- LCD LIDD Csn Address Read/Write Register (Lidd_Csn_Addr)958
- LCD LIDD Csn Address Read/Write Register (Lidd_Csn_Addr) Field Descriptions958
- LCD LIDD Csn Data Read/Write Register (Lidd_Csn_Data)959
- LCD LIDD Csn Data Read/Write Register (Lidd_Csn_Data) Field Descriptions959
- LCD Raster Control Register (RASTER_CTRL)960
- LCD Raster Control Register (RASTER_CTRL) Field Descriptions960
- LCD Controller Data Pin Utilization for Mono/Color Passive/Active Panels962
- Monochrome Passive Mode Pixel Clock and Data Pin Timing963
- Color Passive Mode Pixel Clock and Data Pin Timing963
- Active Mode Pixel Clock and Data Pin Timing964
- TFT Alternate Signal Mapping Output965
- 12-Bit STN Data in Frame Buffer966
- 16-BPP STN Mode966
- LCD Raster Timing Register 0 (RASTER_TIMING_0)967
- LCD Raster Timing Register 0 (RASTER_TIMING_0) Field Descriptions967
- LCD Raster Timing Register 1 (RASTER_TIMING_1)969
- LCD Raster Timing Register 1 (RASTER_TIMING_1) Field Descriptions969
- Vertical Synchronization Pulse Width (VSW) - Active Mode970
- Vertical Front Porch (VFP)971
- Vertical Back Porch (VBP)972
- LCD Raster Timing Register 2 (RASTER_TIMING_2)973
- LCD Raster Timing Register 2 (RASTER_TIMING_2) Field Descriptions973
- SYNC_CTRL = 0, IPC = 1 in TFT Mode975
- SYNC_CTRL = 1, SYNC_EDGE = 0, and IPC = 1976
- LCD Raster Subpanel Display Register (RASTER_SUBPANEL)977
- LCD Raster Subpanel Display Register (RASTER_SUBPANEL) Field Descriptions977
- Subpanel Display: SPEN = 1, HOLS = 1978
- Subpanel Display: SPEN = 1, HOLS = 0978
- LCD DMA Control Register (LCDDMA_CTRL)979
- LCD DMA Control Register (LCDDMA_CTRL) Field Descriptions979
- LCD DMA Frame Buffer N Base Address Register (Lcddma_Fbn_Base)980
- LCD DMA Frame Buffer N Ceiling Address Register (Lcddma_Fbn_Ceiling)980
- LCD DMA Frame Buffer N Base Address Register (Lcddma_Fbn_Base) Field Descriptions980
- LCD DMA Frame Buffer N Ceiling Address Register (Lcddma_Fbn_Ceiling) Field Descriptions980
24 Multichannel Audio Serial Port (Mcasp)981
- Features982
- Protocols Supported983
- Functional Block Diagram984
- Mcasp Block Diagram984
- Mcasp to 6-Channel DAC and 2-Channel DAC985
- Mcasp to Parallel 2-Channel Dacs985
- Mcasp as Digital Audio Encoder986
- Mcasp to Digital Amplifier986
- TDM Format-6 Channel TDM Example987
- Inter-IC Sound (I2S) Format988
- TDM Format Bit Delays from Frame Sync988
- Biphase-Mark Code (BMC)989
- Biphase-Mark Encoder989
- Preamble Codes990
- S/PDIF Subframe Format990
- S/PDIF Frame Format991
- Definition of Bit, Word, and Slot992
  - Definition of Terms992
- Bit Order and Word Alignment Within a Slot Examples993
- Definition of Frame and Frame Sync Width994
  - Overview995
- Transmit Clock Generator Block Diagram996
- Receive Clock Generator Block Diagram997
- Frame Sync Generator Block Diagram998
- Individual Serializer and Connections Within Mcasp999
- Receive Format Unit1000
- Transmit Format Unit1001
- Mcasp I/O Pin Control Block Diagram1003
- Mcasp I/O Pin to Control Register Mapping1004
- Burst Frame Sync Mode1009
- Transmit DMA Event (AXEVT) Generation in TDM Time Slots1012
- Channel Status and User Data for each DIT Block1016
- DSP Service Time Upon Transmit DMA Event (AXEVT)1017
- DSP Service Time Upon Receive DMA Event (AREVT)1018
- DMA Events in an Audio Example-Two Events1020
- Mcasp Audio FIFO (AFIFO) Block Diagram1021
- Transmit Bitstream Data Alignment1023
- Data Flow through Transmit Format Unit1024
- Receive Bitstream Data Alignment1025
- Data Flow through Receive Format Unit1026
- Audio Mute (AMUTE) Block Diagram1028
- Transmit Clock Failure Detection Circuit Block Diagram1032
- Receive Clock Failure Detection Circuit Block Diagram1033
- Serializers in Loopback Mode1034
- EDMA Events - Mcasp1035
  - Reset Considerations1035
- Mcasp Registers Accessed by CPU/EDMA through Peripheral Configuration Port1036
  - Registers1036
- Mcasp AFIFO Registers Accessed through Peripheral Configuration Port1039
  - Register Bit Restrictions1039
- Mcasp Registers Accessed by CPU/EDMA through DMA Port1039
- Revision Identification Register (REV)1040
- Revision Identification Register (REV) Field Descriptions1040
- Pin Function Register (PFUNC)1041
- Pin Function Register (PFUNC) Field Descriptions1042
- Pin Direction Register (PDIR)1043
- Pin Direction Register (PDIR) Field Descriptions1044
- Pin Data Output Register (PDOUT)1045
- Pin Data Output Register (PDOUT) Field Descriptions1046
- Pin Data Input Register (PDIN)1047
- Pin Data Input Register (PDIN) Field Descriptions1048
- Pin Data Set Register (PDSET)1049
- Pin Data Set Register (PDSET) Field Descriptions1050
- Pin Data Clear Register (PDCLR)1051
- Pin Data Clear Register (PDCLR) Field Descriptions1052
- Global Control Register (GBLCTL)1053
- Global Control Register (GBLCTL) Field Descriptions1053
- Audio Mute Control Register (AMUTE)1055
- Audio Mute Control Register (AMUTE) Field Descriptions1055
- Digital Loopback Control Register (DLBCTL)1057
- Digital Loopback Control Register (DLBCTL) Field Descriptions1057
- Digital Mode Control Register (DITCTL)1058
- Digital Mode Control Register (DITCTL) Field Descriptions1058
- Receiver Global Control Register (RGBLCTL)1059
- Receiver Global Control Register (RGBLCTL) Field Descriptions1059
- Receive Format Unit Bit Mask Register (RMASK)1060
- Receive Format Unit Bit Mask Register (RMASK) Field Descriptions1060
- Receive Bit Stream Format Register (RFMT)1061
- Receive Bit Stream Format Register (RFMT) Field Descriptions1061
- Receive Frame Sync Control Register (AFSRCTL)1063
- Receive Frame Sync Control Register (AFSRCTL) Field Descriptions1063
- Receive Clock Control Register (ACLKRCTL)1064
- Receive Clock Control Register (ACLKRCTL) Field Descriptions1064
- Receive High-Frequency Clock Control Register (AHCLKRCTL)1065
- Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions1065
- Receive TDM Time Slot Register (RTDM)1066
- Receive TDM Time Slot Register (RTDM) Field Descriptions1066
- Receiver Interrupt Control Register (RINTCTL)1067
- Receiver Interrupt Control Register (RINTCTL) Field Descriptions1067
- Receiver Status Register (RSTAT)1068
- Receiver Status Register (RSTAT) Field Descriptions1068
- Current Receive TDM Time Slot Registers (RSLOT)1069
- Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions1069
- Receive Clock Check Control Register (RCLKCHK)1070
- Receive Clock Check Control Register (RCLKCHK) Field Descriptions1070
- Receiver DMA Event Control Register (REVTCTL)1071
- Receiver DMA Event Control Register (REVTCTL) Field Descriptions1071
- Transmitter Global Control Register (XGBLCTL)1072
- Transmitter Global Control Register (XGBLCTL) Field Descriptions1072
- Transmit Format Unit Bit Mask Register (XMASK)1073
- Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions1073
- Transmit Bit Stream Format Register (XFMT)1074
- Transmit Bit Stream Format Register (XFMT) Field Descriptions1074
- Transmit Frame Sync Control Register (AFSXCTL)1076
- Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions1076
- Transmit Clock Control Register (ACLKXCTL)1077
- Transmit Clock Control Register (ACLKXCTL) Field Descriptions1077
- Transmit High-Frequency Clock Control Register (AHCLKXCTL)1078
- Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions1078
- Transmit TDM Time Slot Register (XTDM)1079
- Transmit TDM Time Slot Register (XTDM) Field Descriptions1079
- Transmitter Interrupt Control Register (XINTCTL)1080
- Transmitter Interrupt Control Register (XINTCTL) Field Descriptions1080
- Transmitter Status Register (XSTAT)1081
- Transmitter Status Register (XSTAT) Field Descriptions1081
- Current Transmit TDM Time Slot Register (XSLOT)1082
- Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions1082
- Transmit Clock Check Control Register (XCLKCHK)1083
- Transmit Clock Check Control Register (XCLKCHK) Field Descriptions1083
- Transmitter DMA Event Control Register (XEVTCTL)1084
- Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions1084
- Serializer Control Registers (Srctln)1085
- Serializer Control Registers (Srctln) Field Descriptions1085
- DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)1086
- DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)1086
- DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)1087
- DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)1087
- Receive Buffer Registers (Rbufn)1088
- Transmit Buffer Registers (Xbufn)1088
- AFIFO Revision Identification Register (AFIFOREV)1089
- AFIFO Revision Identification Register (AFIFOREV) Field Descriptions1089
- Write FIFO Control Register (WFIFOCTL)1090
- Write FIFO Control Register (WFIFOCTL) Field Descriptions1090
- Write FIFO Status Register (WFIFOSTS)1091
- Write FIFO Status Register (WFIFOSTS) Field Descriptions1091
- Read FIFO Control Register (RFIFOCTL)1092
- Read FIFO Control Register (RFIFOCTL) Field Descriptions1092
- Read FIFO Status Register (RFIFOSTS)1093
- Read FIFO Status Register (RFIFOSTS) Field Descriptions1093
25 Multimedia Card (MMC)/Secure Digital (SD) Card Controller1094
- MMC/SD Card Controller Block Diagram1095
  - Introduction1095
- MMC/SD Controller Interface Diagram1096
- Industry Standard(S) Compliance Statement1096
- MMC Configuration and SD Configuration Diagram1097
  - Clock Control1097
- MMC/SD Controller Clocking Diagram1098
- MMC/SD Controller Pins Used in each Mode1098
  - Signal Descriptions1098
- MMC/SD Mode Write Sequence Timing Diagram1099
- MMC/SD Mode Write Sequence1099
- Protocol Descriptions1099
- MMC/SD Mode Read Sequence Timing Diagram1100
- MMC/SD Mode Read Sequence1100
  - Data Flow in the Input/Output FIFO1100
- FIFO Operation Diagram1101
- Little-Endian Access to MMCDXR/MMCDRR from the CPU or the EDMA1102
  - Data Flow in the Data Registers (MMCDRR and MMCDXR)1102
  - FIFO Operation During Card Read Operation1103
- FIFO Operation During Card Read Diagram1104
  - FIFO Operation During Card Write Operation1105
- FIFO Operation During Card Write Diagram1106
  - Initialization1107
- Description of MMC/SD Interrupt Requests1110
  - Interrupt Support1110
  - DMA Event Support1111
  - Procedures for Common Operations1112
- MMC Card Identification Procedure1113
- SD Card Identification Procedure1114
  - MMC/SD Mode Single-Block Write Operation Using CPU1115
- MMC/SD Mode Single-Block Write Operation1116
  - MMC/SD Mode Single-Block Write Operation Using the EDMA1117
- MMC/SD Mode Single-Block Read Operation1118
  - MMC/SD Mode Single-Block Read Operation Using EDMA1119
- MMC/SD Multiple-Block Write Operation1120
  - MMC/SD Mode Multiple-Block Write Operation Using EDMA1121
- MMC/SD Mode Multiple-Block Read Operation1122
  - MMC/SD Mode Multiple-Block Read Operation Using EDMA1123
- Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers1124
- MMC Control Register (MMCCTL)1125
- MMC Control Register (MMCCTL) Field Descriptions1125
- MMC Memory Clock Control Register (MMCCLK)1126
- MMC Memory Clock Control Register (MMCCLK) Field Descriptions1126
- MMC Status Register 0 (MMCST0)1127
- MMC Status Register 0 (MMCST0) Field Descriptions1127
- MMC Status Register 1 (MMCST1)1129
- MMC Status Register 1 (MMCST1) Field Descriptions1129
- MMC Interrupt Mask Register (MMCIM)1130
- MMC Interrupt Mask Register (MMCIM) Field Descriptions1130
- MMC Response Time-Out Register (MMCTOR)1132
- MMC Response Time-Out Register (MMCTOR) Field Descriptions1132
- MMC Data Read Time-Out Register (MMCTOD)1133
- MMC Data Read Time-Out Register (MMCTOD) Field Descriptions1133
- MMC Block Length Register (MMCBLEN)1134
- MMC Block Length Register (MMCBLEN) Field Descriptions1134
- MMC Number of Blocks Register (MMCNBLK)1135
- MMC Number of Blocks Counter Register (MMCNBLC)1135
- MMC Number of Blocks Register (MMCNBLK) Field Descriptions1135
- MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions1135
- MMC Data Receive Register (MMCDRR)1136
- MMC Data Transmit Register (MMCDXR)1136
- MMC Data Receive Register (MMCDRR) Field Descriptions1136
- MMC Data Transmit Register (MMCDXR) Field Descriptions1136
- MMC Command Register (MMCCMD)1137
- MMC Command Register (MMCCMD) Field Descriptions1137
- Command Format1138
- MMC Argument Register (MMCARGHL)1139
- MMC Argument Register (MMCARGHL) Field Descriptions1139
- MMC Response Register 0 and 1 (MMCRSP01)1140
- MMC Response Register 2 and 3 (MMCRSP23)1140
- MMC Response Register 4 and 5 (MMCRSP45)1140
- MMC Response Register 6 and 7 (MMCRSP67)1140
  - MMC Response Registers (MMCRSP0-MMCRSP7)1140
- R1, R3, R4, R5, or R6 Response (48 Bits)1141
- R2 Response (136 Bits)1141
- MMC Data Response Register (MMCDRSP)1142
- MMC Command Index Register (MMCCIDX)1142
- MMC Data Response Register (MMCDRSP) Field Descriptions1142
- MMC Command Index Register (MMCCIDX) Field Descriptions1142
- SDIO Control Register (SDIOCTL)1143
- SDIO Control Register (SDIOCTL) Field Descriptions1143
- SDIO Status Register 0 (SDIOST0)1144
- SDIO Status Register 0 (SDIOST0) Field Descriptions1144
- SDIO Interrupt Enable Register (SDIOIEN)1145
- SDIO Interrupt Status Register (SDIOIST)1145
- SDIO Interrupt Enable Register (SDIOIEN) Field Descriptions1145
- SDIO Interrupt Status Register (SDIOIST) Field Descriptions1145
- MMC FIFO Control Register (MMCFIFOCTL)1146
- MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions1146
26 Real-Time Clock (RTC)1147
- Real-Time Clock Block Diagram1148
- Introduction1148
- Real-Time Clock Signals1149
  - Architecture1149
  - Operation1150
- 32-Khz Oscillator Counter Compensation1152
  - Interrupt Requests1152
- Kick State Machine1153
  - Register Protection against Spurious Writes1153
  - General-Purpose Scratch Registers1154
- Real-Time Clock (RTC) Registers1155
- Second Register (SECOND)1156
- Minute Register (MINUTE)1156
- Second Register (SECOND) Field Descriptions1156
- Minute Register (MINUTE) Field Descriptions1156
- Hour Register (HOUR)1157
- Hour Register (HOUR) Field Descriptions1157
- Days Register (DAY)1158
- Month Register (MONTH)1158
- Day Register (DAY) Field Descriptions1158
- Month Register (MONTH) Field Descriptions1158
  - Day of the Month Register (DAY)1158
- Year Register (YEAR)1159
- Day of the Week Register (DOTW)1159
- Year Register (YEAR) Field Descriptions1159
- Day of the Week Register (DOTW) Field Descriptions1159
- Alarm Second Register (ALARMSECOND)1160
- Alarm Minute Register (ALARMMINUTE)1160
- Alarm Second Register (ALARMSECOND) Field Descriptions1160
- Alarm Minute Register (ALARMMINUTE) Field Descriptions1160
- Alarm Hour Register (ALARMHOUR)1161
- Alarm Hour Register (ALARMHOUR) Field Descriptions1161
- Alarm Day Register (ALARMDAY)1162
- Alarm Day Register (ALARMDAY) Field Descriptions1162
  - Alarm Day of the Month Register (ALARMDAY)1162
- Alarm Month Register (ALARMMONTH)1163
- Alarm Year Register (ALARMYEAR)1163
- Alarm Month Register (ALARMMONTH) Field Descriptions1163
- Alarm Years Register (ALARMYEARS) Field Descriptions1163
- Control Register (CTRL)1164
- Control Register (CTRL) Field Descriptions1164
- Status Register (STATUS)1165
- Status Register (STATUS) Field Descriptions1165
- Interrupt Register (INTERRUPT)1166
- Interrupt Register (INTERRUPT) Field Descriptions1166
- Compensation (LSB) Register (COMPLSB)1167
- Compensations Register (COMPLSB) Field Descriptions1167
- Compensation (MSB) Register (COMPMSB)1168
- Compensations Register (COMPMSB) Field Descriptions1168
- Oscillator Register (OSC)1169
- Oscillator Register (OSC) Field Descriptions1169
- Scratch Registers (Scratchn)1170
- Kick Registers (Kicknr)1170
- Scratch Registers (Scratchn) Field Descriptions1170
- Kick Registers (Kicknr) Field Descriptions1170
27 Serial Peripheral Interface (SPI)1171
- Introduction1172
- SPI Block Diagram1173
- Functional Block Diagram1173
- SPI Pins1174
- Architecture1174
- SPI Registers1175
  - Programmable Registers1175
- SPI Register Settings Defining Master Modes1176
- Allowed SPI Register Settings in Master Modes1176
  - Master Mode Settings1176
- SPI Register Settings Defining Slave Modes1178
- Allowed SPI Register Settings in Slave Modes1178
  - Slave Mode Settings1178
- SPI 3-Pin Option1179
  - SPI Operation: 3-Pin Mode1179
  - SPI Operation: 4-Pin with Chip Select Mode1180
- SPI 4-Pin Option with Spix_Scs[N]1181
  - SPI Operation: 4-Pin with Enable Mode1182
- SPI 4-Pin Option with Spix_Ena1183
  - SPI Operation: 5-Pin Mode1184
- SPI 5-Pin Option with Spix_Ena and Spix_Scs[N]1185
- Format for Transmitting 12-Bit Word1186
- Format for 10-Bit Received Word1186
  - Data Formats1186
- Clock Mode with POLARITY = 0 and PHASE1187
- Clocking Modes1187
- Clock Mode with POLARITY = 0 and PHASE = 11188
- Clock Mode with POLARITY = 1 and PHASE1188
- Clock Mode with POLARITY = 1 and PHASE = 11188
- Five Bits Per Character (5-Pin Option)1189
  - Interrupt Support1189
  - DMA Events Support1190
  - Reset Considerations1192
  - General-Purpose I/O Pin1193
- SPI 3-Pin Master Mode with WDELAY1194
  - Timing Diagrams1194
- SPI 4-Pin with Spix_Scs[N] Mode with T2CDELAY, WDELAY, and C2TDELAY1195
- SPI 4-Pin with Spix_Ena Mode Demonstrating T2EDELAY and WDELAY1196
- SPI 5-Pin Mode Demonstrating T2CDELAY, T2EDELAY, and WDELAY1198
- SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY1199
- SPI Global Control Register 0 (SPIGCR0)1200
- SPI Registers1200
- SPI Global Control Register 0 (SPIGCR0) Field Descriptions1200
- SPI Global Control Register 1 (SPIGCR1)1201
- SPI Global Control Register 1 (SPIGCR1) Field Descriptions1201
- SPI Interrupt Register (SPIINT0)1203
- SPI Interrupt Register (SPIINT0) Field Descriptions1203
- SPI Interrupt Level Register (SPILVL)1205
- SPI Interrupt Level Register (SPILVL) Field Descriptions1205
- SPI Flag Register (SPIFLG)1206
- SPI Flag Register (SPIFLG) Field Descriptions1206
- SPI Pin Control Register 0 (SPIPC0)1208
- SPI Pin Control Register 0 (SPIPC0) Field Descriptions1208
- SPI Pin Control Register 1 (SPIPC1)1209
- SPI Pin Control Register 1 (SPIPC1) Field Descriptions1209
- SPI Pin Control Register 2 (SPIPC2)1210
- SPI Pin Control Register 2 (SPIPC2) Field Descriptions1210
- SPI Pin Control Register 3 (SPIPC3)1211
- SPI Pin Control Register 3 (SPIPC3) Field Descriptions1211
- SPI Pin Control Register 4 (SPIPC4)1212
- SPI Pin Control Register 4 (SPIPC4) Field Descriptions1212
- SPI Pin Control Register 5 (SPIPC5)1213
- SPI Pin Control Register 5 (SPIPC5) Field Descriptions1213
- SPI Data Register 0 (SPIDAT0)1214
- SPI Data Register 0 (SPIDAT0) Field Descriptions1214
- SPI Data Register 1 (SPIDAT1)1215
- SPI Data Register 1 (SPIDAT1) Field Descriptions1215
- SPI Buffer Register (SPIBUF)1216
- SPI Buffer Register (SPIBUF) Field Descriptions1216
- SPI Emulation Register (SPIEMU)1218
- SPI Emulation Register (SPIEMU) Field Descriptions1218
- SPI Delay Register (SPIDELAY)1219
- SPI Delay Register (SPIDELAY) Field Descriptions1219
  - C2TDELAY = 8 SPI Module Clock Cycles1220
  - T2CDELAY = 4 SPI Module Clock Cycles1221
- Transmit-Data-Finished-To-Spix_Ena-Inactive-Timeout1221
- Chip-Select-Active-To-Spix_Ena-Signal-Active-Timeout1221
- SPI Default Chip Select Register (SPIDEF)1222
- SPI Default Chip Select Register (SPIDEF) Field Descriptions1222
- SPI Data Format Register (Spifmtn)1223
- SPI Data Format Register (Spifmtn) Field Descriptions1223
- SPI Interrupt Vector Register 1 (INTVEC1)1225
- SPI Interrupt Vector Register 1 (INTVEC1) Field Descriptions1225
Bit Timer Plus1226
- Introduction1227
- Timer Block Diagram1228
- Timer Clock Source Block Diagram1229
- Timer Clock Source Selection1229
- 64-Bit Timer Mode Block Diagram1230
- 64-Bit Timer Configurations1231
- Dual 32-Bit Timers Chained Mode Block Diagram1233
- Dual 32-Bit Timers Chained Mode Example1233
- 32-Bit Timer Chained Mode Configurations1234
- Dual 32-Bit Timers Unchained Mode Block Diagram1235
- Dual 32-Bit Timers Unchained Mode Example1236
- 32-Bit Timer Unchained Mode Configurations1237
- 32-Bit Timer Counter Overflow Example1239
- Counter and Period Registers Used in GP Timer Modes1239
- Architecture – Watchdog Timer Mode1240
- Watchdog Timer Mode Block Diagram1241
- Watchdog Timer Operation State Diagram1241
- Reset Considerations1242
- Timer Operation in Pulse Mode (Cpn = 0)1243
- Timer Operation in Clock Mode (Cpn = 1)1243
- TSTAT Parameters in Pulse and Clock Modes1243
  - TM64P_OUT Event Support1243
  - Interrupt/Dma Event Generation Control and Status1244
- Timer Emulation Modes Selection1245
- Timer Registers1245
- Revision ID Register (REVID)1247
- Emulation Management Register (EMUMGT)1247
- Revision ID Register (REVID) Field Descriptions1247
- Emulation Management Register (EMUMGT) Field Descriptions1247
- GPIO Interrupt Control and Enable Register (GPINTGPEN)1248
- GPIO Interrupt Control and Enable Register (GPINTGPEN) Field Descriptions1248
- GPIO Data and Direction Register (GPDATGPDIR)1249
- GPIO Data and Direction Register (GPDATGPDIR) Field Descriptions1249
- Timer Counter Register 12 (TIM12)1250
- Timer Counter Register 34 (TIM34)1250
- Timer Counter Register 12 (TIM12) Field Descriptions1250
- Timer Counter Register 34 (TIM34) Field Descriptions1250
  - Timer Counter Registers (TIM12 and TIM34)1250
- Timer Period Register 12 (PRD12)1251
- Timer Period Register 34 (PRD34)1251
- Timer Period Register (PRD12) Field Descriptions1251
- Timer Period Register (PRD34) Field Descriptions1251
  - Timer Period Registers (PRD12 and PRD34)1251
- Timer Control Register (TCR)1252
- Timer Control Register (TCR) Field Descriptions1252
- Timer Global Control Register (TGCR)1254
- Timer Global Control Register (TGCR) Field Descriptions1254
- Watchdog Timer Control Register (WDTCR)1255
- Watchdog Timer Control Register (WDTCR) Field Descriptions1255
- Timer Reload Register 12 (REL12)1256
- Timer Reload Register 34 (REL34)1256
- Timer Reload Register 12 (REL12) Field Descriptions1256
- Timer Reload Register 34 (REL34) Field Descriptions1256
- Timer Capture Register 12 (CAP12)1257
- Timer Capture Register 34 (CAP34)1257
- Timer Capture Register 12 (CAP12) Field Descriptions1257
- Timer Capture Register 34 (CAP34) Field Descriptions1257
- Timer Interrupt Control and Status Register (INTCTLSTAT)1258
- Timer Interrupt Control and Status Register (INTCTLSTAT) Field Descriptions1258
- Timer Compare Register (Cmpn)1259
- Timer Compare Register (Cmpn) Field Descriptions1259
29 Universal Asynchronous Receiver/Transmitter (UART)1260
- Introduction1261
- UART Block Diagram1262
- UART Clock Generation Diagram1263
  - Peripheral Architecture1263
- Relationships between Data Bit, BCLK, and UART Input Clock1264
- Baud Rate Examples for 150-MHZ UART Input Clock and 16× Over-Sampling Mode1264
- Baud Rate Examples for 150-MHZ UART Input Clock and 13× Over-Sampling Mode1264
- UART Signal Descriptions1265
- UART Protocol Formats1266
- Operation1267
- Character Time for Word Lengths1268
- UART Interface Using Autoflow Diagram1269
- Autoflow Functional Timing Waveforms for Uartn_Rts1270
- Autoflow Functional Timing Waveforms for Uartn_Cts1270
- Reset Considerations1271
- UART Interrupt Request Enable Paths1272
- UART Interrupt Requests Descriptions1272
  - DMA Event Support1273
- UART Registers1274
- Receiver Buffer Register (RBR)1275
- Receiver Buffer Register (RBR) Field Descriptions1275
- Transmitter Holding Register (THR)1276
- Transmitter Holding Register (THR) Field Descriptions1276
- Interrupt Enable Register (IER)1277
- Interrupt Enable Register (IER) Field Descriptions1277
- Interrupt Identification Register (IIR)1278
- Interrupt Identification Register (IIR) Field Descriptions1278
- Interrupt Identification and Interrupt Clearing Information1279
- FIFO Control Register (FCR)1279
- FIFO Control Register (FCR)1280
- FIFO Control Register (FCR) Field Descriptions1280
- Line Control Register (LCR)1281
- Line Control Register (LCR) Field Descriptions1281
- Relationship between ST, EPS, and PEN Bits in LCR1282
- Number of STOP Bits Generated1282
- Modem Control Register (MCR)1283
- Modem Control Register (MCR) Field Descriptions1283
- Line Status Register (LSR)1284
- Line Status Register (LSR) Field Descriptions1284
- Modem Status Register (MSR)1287
- Modem Status Register (MSR) Field Descriptions1287
- Scratch Pad Register (SCR)1288
- Scratch Pad Register (MSR) Field Descriptions1288
- Divisor LSB Latch (DLL)1289
- Divisor MSB Latch (DLH)1289
- Divisor LSB Latch (DLL) Field Descriptions1289
- Divisor MSB Latch (DLH) Field Descriptions1289
- Revision Identification Register 1 (REVID1)1290
- Revision Identification Register 2 (REVID2)1290
- Revision Identification Register 1 (REVID1) Field Descriptions1290
- Revision Identification Register 2 (REVID2) Field Descriptions1290
  - Revision Identification Registers (REVID1 and REVID2)1290
- Power and Emulation Management Register (PWREMU_MGMT)1291
- Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions1291
- Mode Definition Register (MDR)1292
- Mode Definition Register (MDR) Field Descriptions1292
30 Universal Serial Bus OHCI Host Controller1293
- Introduction1294
- Architecture1295
- Open Host Controller Interface Functionality1296
- Implementation of OHCI Specification for USB1.11297
- Relationships between Virtual Address Physical Address1298
  - OHCI Interrupts1298
- USB1.1 Host Controller Registers1299
- HC Operating Mode Register (HCCONTROL)1300
- OHCI Revision Number Register (HCREVISION)1300
- OHCI Revision Number Register (HCREVISION) Field Descriptions1300
- HC Operating Mode Register (HCCONTROL) Field Descriptions1301
- HC Command and Status Register (HCCOMMANDSTATUS)1302
- HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions1302
- HC Interrupt and Status Register (HCINTERRUPTSTATUS)1303
- HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions1303
- HC Interrupt Enable Register (HCINTERRUPTENABLE)1304
- HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions1304
- HC Interrupt Disable Register (HCINTERRUPTDISABLE)1305
- HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions1305
- HC Current Periodic Register (HCPERIODCURRENTED)1306
- HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions1306
- HC HCAA Address Register (HCHCCA)1306
- HC HCAA Address Register (HCHCCA) Field Descriptions1306
- HC Current Control Register (HCCONTROLCURRENTED)1307
- HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions1307
- HC Head Control Register (HCCONTROLHEADED)1307
- HC Head Control Register (HCCONTROLHEADED) Field Descriptions1307
- HC Current Bulk Register (HCBULKCURRENTED)1308
- HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions1308
- HC Head Bulk Register (HCBULKHEADED)1308
- HC Head Bulk Register (HCBULKHEADED) Field Descriptions1308
- HC Frame Interval Register (HCFMINTERVAL)1309
- HC Frame Interval Register (HCFMINTERVAL) Field Descriptions1309
- HC Head Done Register (HCDONEHEAD)1309
- HC Head Done Register (HCDONEHEAD) Field Descriptions1309
- HC Frame Number Register (HCFMNUMBER)1310
- HC Frame Number Register (HCFMNUMBER) Field Descriptions1310
- HC Frame Remaining Register (HCFMREMAINING)1310
- HC Frame Remaining Register (HCFMREMAINING) Field Descriptions1310
- HC Low-Speed Threshold Register (HCLSTHRESHOLD)1311
- HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions1311
- HC Periodic Start Register (HCPERIODICSTART)1311
- HC Periodic Start Register (HCPERIODICSTART) Field Descriptions1311
- HC Root Hub a Register (HCRHDESCRIPTORA)1312
- HC Root Hub a Register (HCRHDESCRIPTORA) Field Descriptions1312
- HC Root Hub B Register (HCRHDESCRIPTORB)1313
- HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions1313
- HC Root Hub Status Register (HCRHSTATUS)1314
- HC Root Hub Status Register (HCRHSTATUS) Field Descriptions1314
- HC Port 1 Status and Control Register (HCRHPORTSTATUS1)1315
- HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions1315
- HC Port 2 Status and Control Register (HCRHPORTSTATUS2)1317
- HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions1317
31 Universal Serial Bus 2.0 (USB) Controller1319
- Introduction1320
  - 31.1.2 Features1320
- Functional Block Diagram1320
  - 31.2 Architecture1321
- USB Clocking Diagram1321
- Industry Standard(S) Compliance Statement1321
- USB Clock Multiplexing Options1322
- PHY PLL Clock Frequencies Supported1322
- USB Terminal Functions1323
  - Signal Descriptions1323
- Interrupt Service Routine Flow Chart1326
- CPU Actions at Transfer Phases1331
- Sequence of Transfer1331
- Service Endpoint 0 Flow Chart1333
- IDLE Mode Flow Chart1334
- TX Mode Flow Chart1335
- RX Mode Flow Chart1336
- PERI_TXCSR Register Bit Configuration for Bulk in Transactions1338
- PERI_RXCSR Register Bit Configuration for Bulk out Transactions1339
- PERI_TXCSR Register Bit Configuration for Isochronous in Transactions1341
- PERI_RXCSR Register Bit Configuration for Isochronous out Transactions1343
- Setup Phase of a Control Transaction Flow Chart1346
- IN Data Phase Flow Chart1348
- OUT Data Phase Flow Chart1350
- Completion of SETUP or out Data Phase Flow Chart1352
- Completion of in Data Phase Flow Chart1354
- USB Controller Block Diagram1361
- Host Packet Descriptor Layout1364
- Host Packet Descriptor Word 0 (HPD Word 0)1364
- Host Packet Descriptor Word 1 (HPD Word 1)1364
- Host Packet Descriptor Word 2 (HPD Word 2)1365
- Host Packet Descriptor Word 3 (HPD Word 3)1365
- Host Packet Descriptor Word 4 (HPD Word 4)1365
- Host Packet Descriptor Word 5 (HPD Word 5)1365
- Host Packet Descriptor Word 6 (HPD Word 6)1366
- Host Packet Descriptor Word 7 (HPD Word 7)1366
- Host Buffer Descriptor Layout1367
- Host Buffer Descriptor Word 0 (HBD Word 0)1367
- Host Buffer Descriptor Word 1 (HBD Word 1)1367
- Host Buffer Descriptor Word 2 (HBD Word 2)1367
- Host Buffer Descriptor Word 3 (HBD Word 3)1367
- Host Buffer Descriptor Word 4 (HBD Word 4)1368
- Host Buffer Descriptor Word 5 (HBD Word 5)1368
- Host Buffer Descriptor Word 6 (HBD Word 6)1368
- Host Buffer Descriptor Word 7 (HBD Word 7)1368
- Teardown Descriptor Layout1369
- Teardown Descriptor Word1369
- Teardown Descriptor Words1369
- Allocation of Queues1370
- Relationship between Memory Regions and Linking RAM1372
- High-Level Transmit and Receive Data Transfer Example1378
- Transmit Descriptors and Queue Status Configuration1379
- Transmit USB Data Flow Example (Initialization)1380
- Transmit USB Data Flow Example (Completion)1381
- Receive Descriptors and Queue Status Configuration1382
- Receive USB Data Flow Example (Initialization)1382
- Receive USB Data Flow Example (Completion)1383
- Interrupts Generated by the USB Controller1384
- USB Interrupt Conditions1384
- USB Interrupts1387
  - Reset Considerations1387
  - Use Cases1388
  - Registers1400
- Universal Serial Bus OTG (USB0) Registers1400
  - Control Register (CTRLR)1407
- Revision Identification Register (REVID)1407
- Revision Identification Register (REVID) Field Descriptions1407
- Control Register (CTRLR) Field Descriptions1407
  - Status Register (STATR)1408
  - Emulation Register (EMUR)1408
- Status Register (STATR) Field Descriptions1408
- Emulation Register (EMUR) Field Descriptions1408
  - Mode Register (MODE)1409
- Mode Register (MODE) Field Descriptions1409
  - Auto Request Register (AUTOREQ)1411
- Auto Request Register (AUTOREQ) Field Descriptions1411
  - SRP Fix Time Register (SRPFIXTIME)1412
  - Teardown Register (TEARDOWN)1412
- SRP Fix Time Register (SRPFIXTIME) Field Descriptions1412
- Teardown Register (TEARDOWN) Field Descriptions1412
  - USB Interrupt Source Register (INTSRCR)1413
- USB Interrupt Source Register (INTSRCR) Field Descriptions1413
- USB Interrupt Source Set Register (INTSETR)1414
- USB Interrupt Source Set Register (INTSETR) Field Descriptions1414
- USB Interrupt Source Clear Register (INTCLRR)1415
- USB Interrupt Source Clear Register (INTCLRR) Field Descriptions1415
- USB Interrupt Mask Register (INTMSKR)1416
- USB Interrupt Mask Register (INTMSKR) Field Descriptions1416
- USB Interrupt Mask Set Register (INTMSKSETR)1417
- USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions1417
- USB Interrupt Mask Clear Register (INTMSKCLRR)1418
- USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions1418
- USB Interrupt Source Masked Register (INTMASKEDR)1419
- USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions1419
- USB End of Interrupt Register (EOIR)1420
- Generic RNDIS EP1 Size Register (GENRNDISSZ1)1420
- USB End of Interrupt Register (EOIR) Field Descriptions1420
- Generic RNDIS EP1 Size Register (GENRNDISSZ1) Field Descriptions1420
- Generic RNDIS EP2 Size Register (GENRNDISSZ2)1421
- Generic RNDIS EP3 Size Register (GENRNDISSZ3)1421
- Generic RNDIS EP2 Size Register (GENRNDISSZ2) Field Descriptions1421
- Generic RNDIS EP3 Size Register (GENRNDISSZ3) Field Descriptions1421
- Generic RNDIS EP4 Size Register (GENRNDISSZ4)1422
- Function Address Register (FADDR)1422
- Generic RNDIS EP4 Size Register (GENRNDISSZ4) Field Descriptions1422
- Function Address Register (FADDR) Field Descriptions1422
- Power Management Register (POWER)1423
- Power Management Register (POWER) Field Descriptions1423
- Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX)1424
- Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (Intrtx)Field Descriptions1424
- Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)1425
- Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions1425
- Interrupt Enable Register for INTRTX (INTRTXE)1426
- Interrupt Enable Register for INTRRX (INTRRXE)1426
- Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions1426
- Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions1426
- Interrupt Register for Common USB Interrupts (INTRUSB)1427
- Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions1427
- Interrupt Enable Register for INTRUSB (INTRUSBE)1428
- Frame Number Register (FRAME)1428
- Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions1428
- Frame Number Register (FRAME) Field Descriptions1428
- Index Register for Selecting the Endpoint Status and Control Registers (INDEX)1429
- Register to Enable the USB 2.0 Test Modes (TESTMODE)1429
- Index Register for Selecting the Endpoint Status and Control Registers (Index)Field Descriptions1429
- Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions1429
- Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)1430
- Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions1430
- Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)1431
- Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions1431
- Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)1432
- Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions1432
- Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)1433
- Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions1433
- Control Status Register for Host Transmit Endpoint (HOST_TXCSR)1434
- Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions1434
- Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)1435
- Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions1435
- Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)1436
- Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions1436
- Control Status Register for Host Receive Endpoint (HOST_RXCSR)1437
- Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions1437
- Count 0 Register (COUNT0)1438
- Receive Count Register (RXCOUNT)1438
- Count 0 Register (COUNT0) Field Descriptions1438
- Receive Count Register (RXCOUNT) Field Descriptions1438
- Type Register (Host Mode Only) (HOST_TYPE0)1439
- Transmit Type Register (Host Mode Only) (HOST_TXTYPE)1439
- Type Register (Host Mode Only) (HOST_TYPE0) Field Descriptions1439
- Transmit Type Register (Host Mode Only) (HOST_TXTYPE) Field Descriptions1439
- Naklimit0 Register (Host Mode Only) (HOST_NAKLIMIT0)1440
- Transmit Interval Register (Host Mode Only) (HOST_TXINTERVAL)1440
- Naklimit0 Register (Host Mode Only) (HOST_NAKLIMIT0) Field Descriptions1440
- Transmit Interval Register (Host Mode Only) (HOST_TXINTERVAL) Field Descriptions1440
- Receive Type Register (Host Mode Only) (HOST_RXTYPE)1441
- Receive Type Register (Host Mode Only) (HOST_RXTYPE) Field Descriptions1441
- Receive Interval Register (Host Mode Only) (HOST_RXINTERVAL)1442
- Receive Interval Register (Host Mode Only) (HOST_RXINTERVAL) Field Descriptions1442
- Configuration Data Register (CONFIGDATA)1443
- Configuration Data Register (CONFIGDATA) Field Descriptions1443
- Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)1444
- Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)1444
- Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions1444
- Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions1444
- Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)1445
- Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)1445
- Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions1445
- Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions1445
- Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)1446
- Device Control Register (DEVCTL)1446
- Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions1446
- Device Control Register (DEVCTL) Field Descriptions1446
- Transmit Endpoint FIFO Size (TXFIFOSZ)1447
- Receive Endpoint FIFO Size (RXFIFOSZ)1447
- Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions1447
- Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions1447
- Transmit Endpoint FIFO Address (TXFIFOADDR)1448
- Receive Endpoint FIFO Address (RXFIFOADDR)1448
- Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions1448
- Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions1448
- Hardware Version Register (HWVERS)1449
- Hardware Version Register (HWVERS) Field Descriptions1449
- Transmit Function Address (TXFUNCADDR)1450
- Transmit Hub Address (TXHUBADDR)1450
- Transmit Hub Port (TXHUBPORT)1450
- Transmit Function Address (TXFUNCADDR) Field Descriptions1450
- Transmit Hub Address (TXHUBADDR) Field Descriptions1450
- Transmit Hub Port (TXHUBPORT) Field Descriptions1450
- Receive Function Address (RXFUNCADDR)1451
- Receive Hub Address (RXHUBADDR)1451
- Receive Hub Port (RXHUBPORT)1451
- Receive Function Address (RXFUNCADDR) Field Descriptions1451
- Receive Hub Address (RXHUBADDR) Field Descriptions1451
- Receive Hub Port (RXHUBPORT) Field Descriptions1451
  - CDMA Revision Identification Register (DMAREVID)1452
  - CDMA Teardown Free Descriptor Queue Control Register (TDFDQ)1452
- CDMA Revision Identification Register (DMAREVID) Field Descriptions1452
- CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) Field Descriptions1452
  - CDMA Emulation Control Register (DMAEMU)1453
  - CDMA Transmit Channel N Global Configuration Registers (TXGCR[0]-TXGCR[3])1453
- CDMA Transmit Channel N Global Configuration Registers (Txgcr[N])1453
- CDMA Emulation Control Register (DMAEMU) Field Descriptions1453
- CDMA Transmit Channel N Global Configuration Registers (Txgcr[N]) Field Descriptions1453
  - CDMA Receive Channel N Global Configuration Registers (RXGCR[0]-RXGCR[3])1454
- CDMA Receive Channel N Global Configuration Registers (Rxgcr[N])1454
- CDMA Receive Channel N Global Configuration Registers (Rxgcr[N]) Field Descriptions1454
  - CDMA Receive Channel N Host Packet Configuration Registers a (RXHPCRA[0]- RXHPCRA[3])1455
- Receive Channel N Host Packet Configuration Registers a (Rxhpcra[N])1455
- Receive Channel N Host Packet Configuration Registers a (Rxhpcra[N]) Field Descriptions1455
  - CDMA Receive Channel N Host Packet Configuration Registers B (RXHPCRB[0]- RXHPCRB[3])1456
- Receive Channel N Host Packet Configuration Registers B (Rxhpcrb[N])1456
- Receive Channel N Host Packet Configuration Registers B (Rxhpcrb[N]) Field Descriptions1456
  - CDMA Scheduler Control Register (DMA_SCHED_CTRL)1457
  - CDMA Scheduler Table Word N Registers (WORD[0]-WORD[63])1457
- CDMA Scheduler Table Word N Registers (Word[N])1457
- CDMA Scheduler Control Register (DMA_SCHED_CTRL) Field Descriptions1457
- CDMA Scheduler Table Word N Registers (Word[N]) Field Descriptions1457
  - Queue Manager Revision Identification Register (QMGRREVID)1459
  - Queue Manager Queue Diversion Register (DIVERSION)1459
- Queue Manager Revision Identification Register (QMGRREVID) Field Descriptions1459
- Queue Manager Queue Diversion Register (DIVERSION) Field Descriptions1459
  - Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0)1460
- Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) Field Descriptions1460
  - Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1)1461
- Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) Field Descriptions1461
  - Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2)1462
- Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) Field Descriptions1462
  - Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3)1463
  - Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE)1463
- Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) Field Descriptions1463
- Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) Field Descriptions1463
  - Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE)1464
  - Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE)1464
- Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) Field Descriptions1464
- Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) Field Descriptions1464
  - Queue Manager Queue Pending Register 0 (PEND0)1465
  - Queue Manager Queue Pending Register 1 (PEND1)1465
- Queue Manager Queue Pending Register 0 (PEND0) Field Descriptions1465
- Queue Manager Queue Pending Register 1 (PEND1) Field Descriptions1465
  - Queue Manager Memory Region R Base Address Registers (QMEMRBASE[0]- QMEMRBASE[15])1466
- Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R])1466
- Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) Field Descriptions1466
  - Queue Manager Memory Region R Control Registers (QMEMRCTRL[0]-QMEMRCTRL[15])1467
- Queue Manager Memory Region R Control Registers (QMEMRCTRL[R])1467
- Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) Field Descriptions1467
  - Queue Manager Queue N Control Register D (CTRLD[0]-CTRLD[63])1468
- Queue Manager Queue N Control Register D (CTRLD[N])1468
- Queue Manager Queue N Control Register D (CTRLD[N]) Field Descriptions1468
  - Queue Manager Queue N Status Register a (QSTATA[0]-QSTATA[63])1469
  - Queue Manager Queue N Status Register B (QSTATB[0]-QSTATB[63])1469
- Queue Manager Queue N Status Register a (QSTATA[N])1469
- Queue Manager Queue N Status Register B (QSTATB[N])1469
- Queue Manager Queue N Status Register a (QSTATA[N]) Field Descriptions1469
- Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions1469
  - Queue Manager Queue N Status Register C (QSTATC[0]-QSTATC[63])1470
- Queue Manager Queue N Status Register C (QSTATC[N])1470
- Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions1470
Revision History1471
- Important Notice1472

Brand	Texas Instruments
Model	TMS320C6745 DSP
Category	Motherboard
Language	English

Texas Instruments TMS320C6745 DSP - User Manual

Table of Contents

Texas Instruments TMS320C6745 DSP Specifications

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