Texas Instruments TMS320C6745 DSP - 10.3 Master Priority Control; Master Ids

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SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.3 Master Priority Control
The on-chip peripherals/modules are essentially divided into two broad categories, masters and slaves.
The master peripherals are typically capable of initiating their own read/write data access requests, this
includes the DSP, EDMA3 transfer controllers, and peripherals that do not rely on the CPU or EDMA3 for
initiating the data transfer to/from them. In order to determine allowed connection between masters and
slave, each master request source must have a unique master ID (mstid) associated with it. The master ID
is shown in Table 10-2. See the device-specific data manual to determine the masters present on your
device.
Each switched central resource (SCR) performs prioritization based on priority level of the master that
sends the read/write requests. For all peripherals/ports classified as masters on the device, the priority is
programmed in the master priority registers (MSTPRI0-3) in the SYSCFG modules. The default priority
levels for each bus master is shown in Table 10-3. Application software is expected to modify these values
to obtain the desired performance.
(1)
This peripheral is not supported on the C6745 DSP.
Table 10-2. Master IDs
Master ID Peripheral
0-1 Reserved
2 DSP MDMA
3 DSP CFG
4-7 Reserved
8 PRU0
9 PRU1
10 TPCC0
11-15 Reserved
16 TPTC0 - read
17 TPTC0 - write
18 TPTC1 - read
19 TPTC1 - write
20-33 Reserved
34 USB2.0 CFG
35 USB2.0 DMA
36 Reserved
37 HPI
(1)
38-63 Reserved
64 EMAC
65 USB1.1
(1)
66-95 Reserved
96 LCDC
(1)
97-255 Reserved