Architecture
www.ti.com
616
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
EMAC/MDIO Module
17.2.17 Power Management
Each of the three main components of the EMAC peripheral can independently be placed in reduced-
power modes to conserve power during periods of low activity. The power management of the EMAC
peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master
controller for power management on behalf of all of the peripherals on the device.
The power conservation modes available for each of the three components of the EMAC/MDIO peripheral
are:
• Idle/Disabled state. This mode stops the clocks going to the peripheral, and prevents all the register
accesses. After reenabling the peripheral from this idle state, all the registers values prior to setting
into the disabled state are restored, and data transmission can proceed. No reinitialization is required.
• Synchronized reset. This state is similar to the Power-on Reset (POR) state, when the processor is
turned-on; reset to the peripheral is asserted, and clocks to the peripheral are gated after that. The
registers are reset to their default value. When powering-up after a synchronized reset, all the EMAC
submodules need to be reinitialized before any data transmission can happen.
For more information on the use of the PSC, see the Power and Sleep Controller (PSC) chapter.
17.2.18 Emulation Considerations
EMAC emulation control is implemented for compatibility with other peripherals. The SOFT and FREE bits
in the emulation control register (EMCONTROL) allow EMAC operation to be suspended.
When the emulation suspend state is entered, the EMAC stops processing receive and transmit frames at
the next frame boundary. Any frame currently in reception or transmission is completed normally without
suspension. For transmission, any complete or partial frame in the transmit cell FIFO is transmitted. For
receive, frames that are detected by the EMAC after the suspend state is entered are ignored. No
statistics are kept for ignored frames.
Table 17-7 shows how the SOFT and FREE bits affect the operation of the emulation suspend.
NOTE: Emulation suspend has not been tested.
Table 17-7. Emulation Control
SOFT FREE Description
0 0 Normal operation
1 0 Emulation suspend
X 1 Normal operation
To Next Page
Loading...
