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Architecture
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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
19.2 Architecture
This section provides details about the architecture and operation of the EMIFB SDRAM interface.
19.2.1 Clock Control
For details on EMIFB clock control, see the Device Clocking chapter.
19.2.2 EMIF Requests
Depending on the specific device, different sources (CPU, EDMA, and other master peripherals) within the
device can make requests to EMIFB. Some of these sources have multiple master ports to the crossbar
(EDMA TPTCs) and some share ports to the crossbar (USB). The requests from these sources consist of
accesses to SDRAM memory and EMIFB registers. The EMIFB implements internal data FIFOs and a
split transaction internal bus to allow concurrence of read and write operations from multiple masters, in
an attempt to fully utilize available throughput of the attached memories.
A high-performance crossbar switch exists within the device to provide prioritized requests from the
different requesters to the EMIFB. If a request is submitted from two or more sources simultaneously, the
crossbar switch will forward the highest priority request to the EMIFB first. Upon completion of a request,
the crossbar switch again evaluates the pending requests and forwards the highest priority pending
request to the EMIFB.
When forwarding read and write commands to the EMIFB, the crossbar uses a priority arbitration scheme.
When the EMIFB receives a request, it may or may not be immediately processed due to prioritization of
pending refresh cycles. In some cases, the EMIFB will perform one or more auto refresh cycles before
processing the request. For details on the EMIFB's internal arbitration between performing requests and
performing auto refresh cycles, see Section 19.2.6.6. For further details regarding master prioritization
within the EMIFB command FIFO, see Section 19.2.6.11.
19.2.3 Pin Descriptions
Table 19-1 describes the function of each EMIFB pin.
Table 19-1. EMIF Pins Used to Access SDRAM
Pins(s) I/O Description
EMB_D[x:0] I/O EMIFB data bus.
The number of available data bus pins varies among devices. See your device-specific data
manual for details.
EMB_A[x:0] O EMIFB address bus.
When interfacing to an SDRAM device, these pins are primarily used to provide the row and
column address to the SDRAM. The number of available address pins depends upon pin
multiplexing configuration. See your device-specific data manual for details. The mapping from the
internal program address to the external values placed on these pins can be found in Table 19-14
and Table 19-15.
EMB_BA[1:0] O EMIFB bank address.
When interfacing to an SDRAM device, these pins are used to provide the bank address inputs to
the SDRAM. The mapping from the internal program address to the external values placed on
these pins can be found in Table 19-14 and Table 19-15.
EMB_WE_DQM[x:0] O Byte enables.
When interfacing to SDRAM, these pins are connected to the DQM pins of the SDRAM to
individually enable/disable each of the bytes in a data access.
EMB_WE O Active-low write enable.
When interfacing to SDRAM, this pin is connected to the WE pin of the SDRAM and is used to
send commands to the device.
EMB_CS O Active-low chip enable pin for SDRAM devices.
This pin is connected to the chip-select pin of the attached SDRAM device and is used for
enabling/disabling commands. By default, the EMIF keeps SDRAM chip select active, even if the
EMIF interface is currently idle.
EMB_RAS O Active-low row address strobe pin.
This pin is connected to the RAS pin of the attached SDRAM device and is used for sending
commands to the device.
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