TI device
I2C
I
2
C
EPROM
I
2
C
I2C
TI device
V
DD
Pull-up
resistors
Serial data (I2Cx_SDA)
Serial clock (I2Cx_SCL)
controller
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Architecture
893
SPRUH91D–March 2013–Revised September 2016
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Inter-Integrated Circuit (I2C) Module
22.2 Architecture
The I2C peripheral consists of the following primary blocks:
• A serial interface: one data pin (I2Cx_SDA) and one clock pin (I2Cx_SCL)
• Data registers to temporarily hold receive data and transmit data traveling between the I2Cx_SDA pin
and the CPU or the EDMA controller
• Control and status registers
• A peripheral data bus interface to enable the CPU and the EDMA controller to access the I2C
peripheral registers
• A clock synchronizer to synchronize the I2C input clock (from the processor clock generator) and the
clock on the I2Cx_SCL pin, and to synchronize data transfers with masters of different clock speeds
• A prescaler to divide down the input clock that is driven to the I2C peripheral
• A noise filter on each of the two pins, I2Cx_SDA and I2Cx_SCL
• An arbitrator to handle arbitration between the I2C peripheral (when it is a master) and another master
• Interrupt generation logic, so that an interrupt can be sent to the CPU
• EDMA event generation logic, so that activity in the EDMA controller can be synchronized to data
reception and data transmission in the I2C peripheral
Figure 24-1 shows the four registers used for transmission and reception. The CPU or the EDMA
controller writes data for transmission to ICDXR and reads received data from ICDRR. When the I2C
peripheral is configured as a transmitter, data written to ICDXR is copied to ICXSR and shifted out on the
I2Cx_SDA pin one bit a time. When the I2C peripheral is configured as a receiver, received data is shifted
into ICRSR and then copied to ICDRR.
22.2.1 Bus Structure
Figure 24-1 shows how the I2C peripheral is connected to the I2C bus. The I2C bus is a multi-master bus
that supports a multi-master mode. This allows more than one device capable of controlling the bus that is
connected to it. A unique address recognizes each I2C device. Each I2C device can operate as either
transmitter or receiver, depending on the function of the device. Devices that are connected to the I2C bus
can be considered a master or slave when performing data transfers, in addition to being a transmitter or
receiver.
NOTE: A master device is the device that initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Any device that is addressed by this master is
considered a slave during this transfer.
An example of multiple I2C modules that are connected for a two-way transfer from one device to other
devices is shown in Figure 22-2.
Figure 22-2. Multiple I2C Modules Connected
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