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SPRUH91D–March 2013–Revised September 2016
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Power and Sleep Controller (PSC)
8.6.14 Power Domain 1 Control Register (PDCTL1)
The power domain 1 control register (PDCTL1) is shown in Figure 8-14 and described in Table 8-19.
Figure 8-14. Power Domain 1 Control Register (PDCTL1)
31 24 23 16
Reserved WAKECNT
R-0 R/W-1Fh
15 12 11 10 9 8 7 1 0
PDMODE Reserved EMUIHBIE Rsvd Reserved NEXT
R-Fh R-0 R/W-0 R-1 R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-19. Power Domain 1 Control Register (PDCTL1) Field Descriptions
Bit Field Value Description
31-24 Reserved 0 Reserved
23-16 WAKECNT 0-FFh RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
15-12 PDMODE 0-Fh Power down mode.
0 Core off, RAM array off, RAM periphery off.
1h Core off, RAM array retention, RAM periphery off (deep sleep).
2h-3h Reserved
4h Core retention, RAM array off, RAM periphery off.
5h Core retention, RAM array retention, RAM periphery off (deep sleep).
6h-7h Reserved
8h Core on, RAM array off, RAM periphery off.
9h Core on, RAM array retention, RAM periphery off (deep sleep).
Ah Core on, RAM array retention, RAM periphery off (light sleep).
Bh Core on, RAM array retention, RAM periphery on.
Ch-Eh Reserved
Fh Core on, RAM array on, RAM periphery on.
11-10 Reserved 0 Reserved
9 EMUIHBIE Emulation alters power domain state interrupt enable.
0 Disable interrupt.
1 Enable interrupt.
8 Reserved 1 Reserved
7-1 Reserved 0 Reserved
0 NEXT User-desired power domain next state.
0 Power domain off.
1 Power domain on.
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