Texas Instruments TMS320C6745 DSP - Chip Signal Clear Register (CHIPSIG_CLR); Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.5.13 Chip Signal Clear Register (CHIPSIG_CLR)
The chip signal clear register (CHIPSIG_CLR) is used to clear the bits set in the chip signal register
(CHIPSIG). Writing a 1 to a CHIPSIG[n] bit in CHIPSIG_CLR clears the corresponding CHIPSIG[n] bit in
CHIPSIG; writing a 0 has no effect. After servicing the interrupt, the interrupted processor can clear the
bits set in CHIPSIG by writing 1 to the corresponding bits in CHIPSIG_CLR. The other processor may poll
the CHIPSIG[n] bit to determine when the interrupted processor has completed the interrupt service. The
CHIPSIG_CLR is shown in Figure 10-40 and described in Table 10-44.
For more information on DSP interrupts, see the DSP Subsystem chapter.
Figure 10-40. Chip Signal Clear Register (CHIPSIG_CLR)
31 16
Reserved
R-0
15 5 4 3 2 1 0
Reserved CHIPSIG4 CHIPSIG3 CHIPSIG2 Reserved
R-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-44. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reserved
4 CHIPSIG4 Clears DSP NMI interrupt.
0 No effect
1 Clears interrupt
3 CHIPSIG3 Clears SYSCFG_CHIPINT3 interrupt.
0 No effect
1 Clears interrupt
2 CHIPSIG2 Clears SYSCFG_CHIPINT2 interrupt.
0 No effect
1 Clears interrupt
1-0 Reserved 0 Reserved. Write the default value to all bits when modifying this register.