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SYSCFG Registers
181
SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.5.7 Interrupt Registers
The interrupt registers are a set of registers that provide control for the address and protection violation
error interrupt generated by the SYSCFG module when there is an address or protection violation to the
module's memory-mapped register address space. This includes enable control, interrupt set and clear
control, and end of interrupt (EOI) control.
10.5.7.1 Interrupt Raw Status/Set Register (IRAWSTAT)
The interrupt raw status/set register (IRAWSTAT) shows the interrupt status before enabling the interrupt
and allows setting of the interrupt status. The IRAWSTAT is shown in Figure 10-8 and described in
Table 10-12.
Figure 10-8. Interrupt Raw Status/Set Register (IRAWSTAT)
31 16
Reserved
R-0
15 2 1 0
Reserved ADDRERR PROTERR
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-12. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved. Always read 0.
1 ADDRERR Addressing violation error. Reading this bit field reflects the raw status of the interrupt before
enabling.
0 Indicates the interrupt is not set. Writing 0 has no effect.
1 Indicates the interrupt is set. Writing 1 sets the status.
0 PROTERR Protection violation error. Reading this bit field reflects the raw status of the interrupt before enabling.
0 Indicates the interrupt is not set. Writing 0 has no effect.
1 Indicates the interrupt is set. Writing 1 sets the status.
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