Texas Instruments TMS320C6745 DSP - Chip Configuration 2 Register (CFGCHIP2); Chip Configuration 2 Register (CFGCHIP2) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.5.16 Chip Configuration 2 Register (CFGCHIP2)
The chip configuration 2 register (CFGCHIP2) controls the following functions:
• USB1.1 OHCI (this peripheral is not supported on the C6745 DSP.)
• USB2.0 OTG PHY
The CFGCHIP2 is shown in Figure 10-43 and described in Table 10-47.
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Figure 10-43. Chip Configuration 2 Register (CFGCHIP2)
31 24
Reserved
R-0
23 18 17 16
Reserved USB0PHYCLKGD USB0VBUSSENSE
R-0 R-0 R-0
15 14 13 12 11 10 9 8
RESET USB0OTGMODE USB1PHYCLKMUX
(1)
USB0PHYCLKMUX USB0PHYPWDN USB0OTGPWRDN USB0DATPOL
R/W-1 R/W-3h R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
7 6 5 4 3 0
USB1SUSPENDM
(1)
USB0PHY_PLLON USB0SESNDEN USB0VBDTCTEN USB0REF_FREQ
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reserved
17 USB0PHYCLKGD Status of USB2.0 PHY.
0 Clock is not present, power is not good, and PLL has not locked.
1 Clock is present, power is good, and PLL has locked.
16 USB0VBUSSENSE Status of USB2.0 PHY VBUS sense.
0 PHY is not sensing voltage presence on the VBUS pin.
1 PHY is sensing voltage presence on the VBUS pin.
15 RESET USB2.0 PHY reset.
0 Not in reset
1 USB2.0 PHY in reset
14-13 USB0OTGMODE USB2.0 OTG subsystem mode.
0 No override. PHY drive signals to controller based on its comparators for VBUS and ID pins.
1h Override phy values to force USB host operation.
2h Override phy values to force USB device operation.
3h Override phy values to force USB host operation with VBUS low.
12 USB1PHYCLKMUX USB1.1 PHY reference clock input mux. Controls clock mux to USB1.1. This peripheral is
not supported on the C6745 DSP.
0 USB1.1 PHY reference clock is sourced by output of USB2.0 PHY.
1 USB1.1 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.
11 USB0PHYCLKMUX USB2.0 PHY reference clock input mux.
0 USB2.0 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.
1 USB2.0 PHY reference clock (AUXCLK) is internally generated from the PLL.