Texas Instruments TMS320C6745 DSP - SYSCLK Status Register (SYSTAT); SYSCLK Status Register (SYSTAT) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Phase-Locked Loop Controller (PLLC)
7.4.22 SYSCLK Status Register (SYSTAT)
The SYSCLK status register (SYSTAT) is shown in Figure 7-23 and described in Table 7-24. Indicates
SYSCLK on/off status. Actual default is determined by actual clock on/off status, which depends on the
DnEN bit in PLLDIVn default.
Figure 7-23. SYSCLK Status Register (SYSTAT)
31 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved SYS7ON SYS6ON SYS5ON SYS4ON SYS3ON SYS2ON SYS1ON
R-0 R-1 R-1 R-1 R-1 R-1 R-1 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-24. SYSCLK Status Register (SYSTAT) Field Descriptions
Bit Field Value Description
31-7 Reserved 0 Reserved
6 SYS7ON SYSCLK7 on status
0 Off
1 On
5 SYS6ON SYSCLK6 on status
0 Off
1 On
4 SYS5ON SYSCLK5 on status
0 Off
1 On
3 SYS4ON SYSCLK4 on status
0 Off
1 On
2 SYS3ON SYSCLK3 on status
0 Off
1 On
1 SYS2ON SYSCLK2 on status
0 Off
1 On
0 SYS1ON SYSCLK1 on status
0 Off
1 On