PSC Registers
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SPRUH91D–March 2013–Revised September 2016
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Power and Sleep Controller (PSC)
8.6.10 Power Domain Transition Status Register (PTSTAT)
The power domain transition status register (PTSTAT) is shown in Figure 8-10 and described in
Table 8-15 .
Figure 8-10. Power Domain Transition Status Register (PTSTAT)
31 16
Reserved
R-0
15 2 1 0
Reserved GOSTAT[1] GOSTAT[0]
R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 8-15. Power Domain Transition Status Register (PTSTAT) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 GOSTAT[1] RAM/Pseudo (PD1) power domain transition status.
0 No transition in progress.
1 RAM/Pseudo power domain is transitioning (that is, either the power domain is transitioning or modules
in this power domain are transitioning).
0 GOSTAT[0] Always ON (PD0) power domain transition status.
0 No transition in progress.
1 Modules in Always ON power domain are transitioning. Always On power domain is transitioning.