Texas Instruments TMS320C6745 DSP - OBSCLK Select Register (OCSEL); OBSCLK Select Register (OCSEL) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Phase-Locked Loop Controller (PLLC)
7.4.4 OBSCLK Select Register (OCSEL)
NOTE: This register is not supported on the C6745 DSP.
The OBSCLK select register (OCSEL) controls which clock is output on the OBSCLK pin so that it may be
used for test and debug purposes (in addition to its normal function of being a direct input clock divider).
The OCSEL is shown in Figure 7-5 and described in Table 7-6.
Figure 7-5. OBSCLK Select Register (OCSEL)
31 16
Reserved
R-0
15 5 4 0
Reserved OCSRC
R-0 R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-6. OBSCLK Select Register (OCSEL) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reserved
4-0 OCSRC 0-1Fh OBSCLK source. Output on OBSCLK pin.
0-13h Reserved
14h OSCIN
15h-16h Reserved
17h PLLC0 SYSCLK1
18h PLLC0 SYSCLK2
19h PLLC0 SYSCLK3
1Ah PLLC0 SYSCLK4
1Bh PLLC0 SYSCLK5
1Ch PLLC0 SYSCLK6
1Dh PLLC0 SYSCLK7
1Eh Reserved
1Fh Disabled