www.ti.com
Registers
513
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.1.4 DMA Channel Queue Number Register n (DMAQNUMn)
The DMA channel queue number register n (DMAQNUMn) allows programmability of each of the 32 DMA
channels in the EDMA3CC to submit its associated synchronization event to any event queue in the
EDMA3CC. At reset, all channels point to event queue 0. The DMAQNUMn is shown in Figure 16-46 and
described in Table 16-24. Table 16-25 shows the channels and their corresponding bits in DMAQNUMn.
NOTE: Since the event queues in EDMA3CC have a fixed association to the transfer controllers,
that is, Q0 TRs are submitted to TC0 and Q1 TRs are submitted to TC1, by programming
DMAQNUMn for a particular DMA channel also dictates which transfer controller is utilized
for the data movement (or which EDMA3TC receives the TR request).
Figure 16-46. DMA Channel Queue Number Register n (DMAQNUMn)
31 30 28 27 26 24 23 22 20 19 18 16
Rsvd En Rsvd En Rsvd En Rsvd En
R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 R-0 R/W-0
15 14 12 11 10 8 7 6 4 3 2 0
Rsvd En Rsvd En Rsvd En Rsvd En
R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-24. DMA Channel Queue Number Register n (DMAQNUMn) Field Descriptions
Bit Field Value Description
31-0 En 0-7h DMA queue number. Contains the event queue number to be used for the corresponding DMA channel.
Programming DMAQNUMn for an event queue number to a value more then the number of queues
available in the EDMA3CC results in undefined behavior.
0 Event n is queued on Q0.
1h Event n is queued on Q1.
2h-7h Reserved
Table 16-25. Bits in DMAQNUMn
En bit
DMAQNUMn
0 1 2 3
0-2 E0 E8 E16 E24
4-6 E1 E9 E17 E25
8-10 E2 E10 E18 E26
12-14 E3 E11 E19 E27
16-18 E4 E12 E20 E28
20-22 E5 E13 E21 E29
24-26 E6 E14 E22 E30
28-30 E7 E15 E23 E31
To Next Page