MPU Registers
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SPRUH91D–March 2013–Revised September 2016
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Memory Protection Unit (MPU)
5.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
The fixed range memory protection page attributes register (FXD_MPPA) holds the permissions for the
fixed region. This register is writeable by a supervisor entity only. The FXD_MPPA is shown in Figure 5-11
and described in Table 5-14.
Figure 5-11. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
31 26 25 22 21 20 19 18 17 16
Reserved Reserved AID11 AID10 AID9 AID8 AID7 AID6
R-0 R-Fh R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AID5 AID4 AID3 AID2 AID1 AID0 AIDX Rsvd Rsvd Rsvd SR SW SX UR UW UX
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-14. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
Field Descriptions
Bit Field Value Description
31-26 Reserved 0 Reserved
25-22 Reserved Fh Reserved
21-10 AIDn Controls access from ID = n.
0 Access is denied.
1 Access is granted.
9 AIDX Controls access from ID > 11.
0 Access is denied.
1 Access is granted.
8 Reserved 0 Reserved
7 Reserved 1 Reserved. This bit must be written as 1.
6 Reserved 1 Reserved. This bit must be written as 1.
5 SR Supervisor Read permission.
0 Access is denied.
1 Access is allowed.
4 SW Supervisor Write permission.
0 Access is denied.
1 Access is allowed.
3 SX Supervisor Execute permission.
0 Access is denied.
1 Access is allowed.
2 UR User Read permission.
0 Access is denied.
1 Access is allowed.
1 UW User Write permission.
0 Access is denied.
1 Access is allowed.
0 UX User Execute permission.
0 Access is denied.
1 Access is allowed.
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