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903
SPRUH91D–March 2013–Revised September 2016
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Inter-Integrated Circuit (I2C) Module
22.2.11.1 Configuring the I2C in Master Receiver Mode and Servicing Receive Data via CPU
The following initialization procedure is for the I2C controller configured in Master Receiver mode. The
CPU is used to move data from the I2C receive register to CPU memory (memory accessible by the
CPU).
1. Enable I2C clock from the Power and Sleep Controller, if it is driven by the Power and Sleep Controller
(see the Power and Sleep Controller (PSC) chapter).
2. Place I2C in reset (clear IRS = 0 in ICMDR).
3. Configure ICMDR:
• Configure I2C as Master (MST = 1).
• Indicate the I2C configuration to be used; for example, Data Receiver (TRX = 0)
• Indicate 7-bit addressing is to be used (XA = 0).
• Disable repeat mode (RM = 0).
• Disable loopback mode (DLB = 0).
• Disable free data format (FDF = 0).
• Optional: Disable start byte mode if addressing a fully fledged I2C device (STB = 0).
• Set number of bits to transfer to be 8 bits (BC = 0).
4. Configure Slave Address: the I2C device this I2C master would be addressing (ICSAR = 7BIT
ADDRESS).
5. Configure the peripheral clock operation frequency (ICPSC). This value should be selected in such a
way that the frequency is between 6.7 and 13.3 MHz.
6. Configure I2C master clock frequency:
• Configure the low-time divider value (ICCLKL).
• Configure the high-time divider value (ICCLKH).
7. Make sure the interrupt status register (ICSTR) is cleared:
• Read ICSTR and write it back (write 1 to clear) ICSTR = ICSTR
• Read ICIVR until it is 0.
8. Take I2C controller out of reset: enable I2C controller (set IRS bit = 1 in ICMDR).
9. Wait until bus busy bit is cleared (BB = 0 in ICSTR).
10. Generate a START event, followed by Slave Address, etc. (set STT = 1 in ICMDR).
11. Wait until data is received (ICRRDY = 1 in ICSTR).
12. Read data:
• If ICRRDY = 1 in ICSTR, then read ICDRR.
• Perform the previous two steps until receiving one byte short of the entire byte expecting to
receive.
13. Configure the I2C controller not to generate an ACK on the next/final byte reception: set NACKMOD
bit for the I2C to generate a NACK on the last byte received (set NACKMOD = 1 in ICMDR).
14. End transfer/release bus when transfer is done. Generate a STOP event (set STP = 1 in ICMDR).
22.2.12 Interrupt Support
The I2C peripheral is capable of interrupting the CPU. The CPU can determine which I2C events caused
the interrupt by reading the I2C interrupt vector register (ICIVR). ICIVR contains a binary-coded interrupt
vector type to indicate which interrupt has occurred. Reading ICIVR clears the interrupt flag; if other
interrupts are pending, a new interrupt is generated. If there is more than one pending interrupt flag,
reading ICIVR clears the highest-priority interrupt flag.
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