Texas Instruments TMS320C6745 DSP - 10.2 Protection; System Configuration (SYSCFG) Module Register Access

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SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.2 Protection
Table 10-1 provides the list of registers in the SYSCFG module; it also indicates whether a particular
register can be accessed only when the CPU is in privileged mode. See Section 10.5 for a description of
these registers.
Table 10-1. System Configuration (SYSCFG) Module Register Access
Offset Acronym Register Description Access
0h REVID Revision Identification Register —
8h-14h DIEIDR0-DIEIDR3 Die Identification 0-3 Registers —
18h DEVIDR0 Device Identification Register 0 —
20h BOOTCFG Boot Configuration Register Privileged mode
24h CHIPREVID Silicon Revision Identification Register Privileged mode
38h KICK0R Kick 0 Register Privileged mode
3Ch KICK1R Kick 1 Register Privileged mode
44h HOST1CFG Host 1 Configuration Register —
E0h IRAWSTAT Interrupt Raw Status/Set Register Privileged mode
E4h IENSTAT Interrupt Enable Status/Clear Register Privileged mode
E8h IENSET Interrupt Enable Register Privileged mode
ECh IENCLR Interrupt Enable Clear Register Privileged mode
F0h EOI End of Interrupt Register Privileged mode
F4h FLTADDRR Fault Address Register Privileged mode
F8h FLTSTAT Fault Status Register —
110h-118h MSTPRI0-MSTPRI2 Master Priority 0-2 Registers Privileged mode
120h-16Ch PINMUX0-PINMUX19 Pin Multiplexing Control 0-19 Registers Privileged mode
170h SUSPSRC Suspend Source Register Privileged mode
174h CHIPSIG Chip Signal Register —
178h CHIPSIG_CLR Chip Signal Clear Register —
17Ch-18Ch CFGCHIP0-CFGCHIP4 Chip Configuration 0-4 Registers Privileged mode