Texas Instruments TMS320C6745 DSP - Memory Map

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SPRUH91D–March 2013–Revised September 2016
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DSP Subsystem
Static power-down (clock gating) affects all components of the C674x megamodule and all internal
memories. Software can initiate static power-down by way of a register bit in the power-down controller
command register (PDCCMD) of the PDC. For more information on the PDC, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
2.2.2.3 Bandwidth Manager (BWM)
The bandwidth manager (BWM) provides a programmable interface for optimizing bandwidth among the
requesters for resources, which include the following:
• EDMA3-initiated DMA transfers (and resulting coherency operations)
• DSP subsystem IDMA-initiated transfers (and resulting coherency operations)
• Programmable cache coherency operations
– Block based coherency operations
– Global coherency operations
• CPU direct-initiated transfers
– Data access (load/store)
– Program access
The resources include the following:
• L1P memory
• L1D memory
• L2 memory
• Resources outside of the C674x megamodule: external memory, on-chip peripherals, registers
Since any given requestor could potentially block a resource for extended periods of time, the bandwidth
manager is implemented to assure fairness for all requesters.
The bandwidth manager implements a weighted-priority-driven bandwidth allocation. Each requestor
(EDMA, IDMA, CPU, etc.) is assigned a priority level on a per-transfer basis. The programmable priority
level has a single meaning throughout the system. There are a total of nine priority levels, where priority
zero is the highest priority and priority eight is the lowest priority. When requests for a single resource
contend, access is granted to the highest-priority requestor. When the contention occurs for multiple
successive cycles, a contention counter assures that the lower-priority requestor gets access to the
resource every 1 out of n arbitration cycles, where n is programmable. A priority level of -1 represents a
transfer whose priority has been increased due to expiration of the contention counter or a transfer that is
fixed as the highest-priority transfer to a given resource.
2.2.2.4 Internal DMA (IDMA) Controller
The IDMA controller performs fast block transfers between any two memory locations local to the C674x
megamodule. Local memory locations are defined as those in Level 1 program (L1P), Level 1 data (L1D),
and Level 2 (L2) memories, or in the external peripheral configuration (CFG) memory. The IDMA cannot
transfer data to or from the internal DSP memory-mapped register space. The IDMA is fully described in
the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
2.3 Memory Map
Refer to your device-specific data manual for memory-map information.
2.3.1 DSP Internal Memory
See the System Memory chapter for a description of the DSP internal memory.
2.3.2 External Memory
See the System Interconnect chapter and the System Memory chapter for a description of the additional
system memory and peripherals that the DSP has access to.